ICS9FG107 Datasheet, PDF (5/14 Pages) Integrated Circuit Systems – Programmable FTG for Differential CPU, PCI Express & SATA Clocks

Integrated
Circuit
Systems, Inc.
ICS9FG107
Absolute Max
Symbol
Parameter
VDD_A
3.3V Core Supply Voltage
VDD_In 3.3V Logic Input Supply Voltage
Ts
Tambient
Tcase
ESD prot
Storage Temperature
Ambient Operating Temp
Case Temperature
Input ESD protection
human body model
Min
GND - 0.5
-65
0
2000
Max
V_DD + 0.5V
V_DD + 0.5V
150
70
115
Units
V
V
°_C
°C
°C
V
Electrical Characteristics - Input/Supply/Common Output Parameters
T_A = 0 - 70°C; Supply Voltage V_DD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
V_IH
3.3 V +/-5%
2
V_IL
3.3 V +/-5%
V_SS - 0.3
I_IH
V_IN = V_DD
-5
I_IL1
V_IN = 0 V; Inputs with no pull-
up resistors
-5
I_IL2
V_IN = 0 V; Inputs with pull-up
-200
resistors
Operating Supply Current I_DD3.3OP
Full Active, C_L = Full load;
f = 400 MHz
Full Active, C_L = Full load;
f = 100 MHz
Input Frequency³
F_i
V_DD = 3.3 V
14
Pin Inductance¹
L_pin
Input/Output
Capacitance¹
C_IN
Logic Inputs
1.5
C_OUT
Output pin capacitance
Clk Stabilization^1,2
T_STAB
From V_DD Power-Up and after
input clock stabilization to 1st
clock
Modulation Frequency
f_MOD
Triangular Modulation
30
DIF output enable
t_DIFOE
DIF output enable after
DIF_Stop# de-assertion
MAX UNITS NOTES
V_DD + 0.3 V
0.8
V
5
uA
uA
uA
250
mA
200
mA
25
MHz 3
7
nH
1
5
pF
1
6
pF
1
1.8
ms 1,2
40
kHz
1
10
ns
1
Input Rise and Fall times t_R/t_F
20% to 80% of VDD
5
ns
1
1_{Guaranteed by design and characterization, not 100% tested in production.}
2_{See timing diagrams for timing requirements.}
3 _{Input frequency should be measured at the REFOUT pin and tuned to ideal 14.31818MHz or 25 MHz to meet}
ppm frequency accuracy on PLL outputs.
0863C—11/22/04
5