ICS9FG107 Datasheet, PDF (2/14 Pages) Integrated Circuit Systems – Programmable FTG for Differential CPU, PCI Express & SATA Clocks

Integrated
Circuit
Systems, Inc.
ICS9FG107
Pin Description
PIN
#
PIN NAME
1 XIN/CLKIN
2 X2
3 VDD
4 GND
5 *FS2/REFOUT
6 GND
7 *FS0/PCICLK_F
8 PCICLK0
9 PCICLK1
10 VDD
11 **OE_6
12 DIF_6
13 DIF_6#
14 VDD
15 GND
16 **OE_5
17 DIF_5
18 DIF_5#
19 VDD
20 DIF_4
21 DIF_4#
22 *OE_4
23 SDATA
24 SCLK
PIN TYPE
DESCRIPTION
IN
OUT
PWR
PWR
I/O
PWR
Crystal input or Reference Clock input
Crystal output, Nominally 14.318MHz
Power supply, nominal 3.3V
Ground pin.
Frequency select latch input pin / Reference clock output
Ground pin.
I/O Frequency select latch input pin / 3.3V PCI free running clock output.
OUT
OUT
PWR
IN
OUT
OUT
PWR
PWR
IN
OUT
OUT
PWR
OUT
OUT
IN
I/O
IN
PCI clock output.
PCI clock output.
Power supply, nominal 3.3V
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
0.7V differential true clock outputs
0.7V differential complement clock outputs
Power supply, nominal 3.3V
Ground pin.
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
0.7V differential true clock outputs
0.7V differential complement clock outputs
Power supply, nominal 3.3V
0.7V differential true clock outputs
0.7V differential complement clock outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
Data pin for SMBus circuitry, 5V tolerant.
Clock pin of SMBus circuitry, 5V tolerant.
0863C—11/22/04
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