ICS9FG107 Datasheet, PDF (12/14 Pages) Integrated Circuit Systems – Programmable FTG for Differential CPU, PCI Express & SATA Clocks

Integrated
Circuit
Systems, Inc.
ICS9FG107
DIF_STOP# - Assertion (transition from '1' to '0')
Asserting DIF_STOP# pin stops all DIF outputs that are set to be stoppable after their next transition. When the I2C
DIF_STOP tri-state bit corresponding to the DIF output of interest is programmed to a '0', DIF output will stop DIF_True =
HIGH and DIF_Complement = LOW. When the I2C DIF_STOP tri-state bit corresponding to the DIF output of interest is
programmed to a '1', DIFoutputs will be tri-stated.
DIF_STOP#
DIF
DIF#
DIF_STOP# - De-assertion (transition from '0' to '1')
With the de-assertion of DIF_STOP# all stopped DIF outputs will resume without a glitch. The maximum latency from the
de-assertion to active outputs is 2 - 6 DIF clock periods. If the control register tristate bit corresponding to the output of
interest is programmed to '1', then the stopped DIF outputs will be driven High within 10nS of DIF_Stop# de-assertion to a
voltage greater than 200mV.
DIF_Stop#
DIF
DIF#
DIF Internal
Tdrive_DIF_Stop, 10nS >200mV
0863C—11/22/04
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