ICS952802 Datasheet, PDF (9/19 Pages) Integrated Circuit Systems – Programmable Timing Control Hu for P4 processor

Integrated
Circuit
Systems, Inc.
I²C Table: VCO Frequency Control Register
Byte 12
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
-
-
-
-
-
-
-
Name
N Div7
N Div6
N Div5
N Div4
N Div3
N Div2
N Div1
N Div0
Control
Function
The decimal
representation of N Div
(8:0) + 8 is equal to
VCO divider value.
Default at power up =
latch-in or Byte 0 Rom
table.
Type
RW
RW
RW
RW
RW
RW
RW
RW
ICS952802
Advance Information
0
1
PWD
-
-
X
-
-
X
-
-
X
-
-
X
-
-
X
-
-
X
-
-
X
-
-
X
I²C Table: Spread Spectrum Control Register
Byte 13
Pin #
Name
Control
Function
Type
0
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
SSP7
RW
-
SSP6
These Spread
RW
-
SSP5
Spectrum bits will
RW
-
SSP4
program the spread
pecentage. It is
RW
-
SSP3
recommended to use
RW
-
SSP2
ICS Spread % table for
RW
-
SSP1
spread programming.
RW
-
SSP0
RW
-
1
PWD
-
X
-
X
-
X
-
X
-
X
-
X
-
X
-
X
I²C Table: Spread Spectrum Control Register
Byte 14
Pin #
Name
Control
Function
Type
0
Bit 7
-
Reserved
Reserved
R
-
Bit 6
-
Reserved
Reserved
R
-
Bit 5
-
SSP13
R
-
Bit 4
-
SSP12
It is recommended to
RW
-
Bit 3
-
SSP11
use ICS Spread %
RW
-
Bit 2
-
Bit 1
-
SSP10
Table for Spread
RW
-
SSP9
Programming
RW
-
Bit 0
-
SSP8
RW
-
1
PWD
-
0
-
0
-
X
-
X
-
X
-
X
-
X
-
X
I²C Table: Output Divider Control Register
Byte 15
Pin #
Name
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
PCI Div3
PCI Div2
PCI Div1
PCI Div0
CPU Div3
CPU Div2
CPU Div1
CPU Div0
Control
Function
PCI divider ratio can be
configured via these 4
bits individually.
CPU divider ratio can
be configured via these
4 bits individually.
0731—09/18/02
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
See Table 2: Divider Ratio
Combination Table
See Table 2: Divider Ratio
Combination Table
PWD
X
X
X
X
X
X
X
X
9