ICS952802 Datasheet, PDF (2/19 Pages) Integrated Circuit Systems – Programmable Timing Control Hu for P4 processor

Integrated
Circuit
Systems, Inc.
ICS952802
Advance Information
General Description
The ICS952802 is a two chip clock solution for desktop designs using SIS 755/760 style chipsets. When used with a zero
delay buffer such as the ICS9179-16 for PC133 or the ICS93735 for DDR applications it provides all the necessary clocks
signals for such a system.
The ICS952802 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). ICS is the
first to introduce a whole product line which offers full programmability and flexibility on a single clock device. Employing the
use of a serially programmable I²C interface, this device can adjust the output clocks by configuring the frequency setting, the
output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each
individual output clock. TCH also incorporates ICS's Watchdog Timer technology and a reset feature to provide a safe setting
under unstable system conditions. M/N control can configure output frequency with resolution up to 0.1MHz increment.
Block Diagram
X1
XTAL
X2
PLL2
Frequency
Dividers
PD#
CPU_STOP#
PCI_STOP#
FS (4:0)
SEL24_48#
SEL12_48#
SELPCI_12#
Control
Logic
Programmable
Spread
PLL1
Programmable
Frequency
Dividers
STOP
Logic
12_48MHz
24_48MHz
PCI7_12MHZ
REF (2:0)
CPUCLK8T (1:0)
CPUCLK8C (1:0)
AGPCLK (1:0)
PCICLK (8,6:0)
PCICLKF (1:0)
RESET#
0731—09/18/02
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