ICS952802 Datasheet, PDF (10/19 Pages) Integrated Circuit Systems – Programmable Timing Control Hu for P4 processor

Integrated
Circuit
Systems, Inc.
ICS952802
Advance Information
Table2: Divider Ratio Combination Table
Divider (3:2)
Bit
00
01
10
1
2
00
0000
2
0100
4
1000
01
0001
3
0101
6
1001
10
0010
5
0110
10
1010
11
0011
7
0111
14
1011
LSB
Address
Div
Address
Div
Address
I²C Table: Output Divider Control Register
Byte 16
Pin #
Name
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
AGPDiv3
AGPDiv2
AGPDiv1
AGPDiv0
ZCLKDiv3
ZCLKDiv2
ZCLKDiv1
ZCLKDiv0
Control
Function
AGP divider ratio can
be configured via these
4 bits individually.
ZCLK divider ratio can
be configured via these
4 bits individually.
Type
RW
RW
RW
RW
RW
RW
RW
RW
11
MSB
4
8
8
1100
16
12
1101
24
20
1110
40
28
1111
56
Div
Address
Div
0
1
See Table 2: Divider Ratio
Combination Table
See Table 2: Divider Ratio
Combination Table
PWD
X
X
X
X
X
X
X
X
I²C Table: Output Divider Control Register
Byte 17
Pin #
Name
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
AGPINV
ZCLKSDINV
Reserved
CPUINV
Reserved
Reserved
Reserved
Reserved
Control
Function
AGPPhase Invert
ZCLK Phase Invert
Reserved
CPU Phase Invert
Reserved
Reserved
Reserved
Reserved
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Default
Default
-
Default
-
-
-
-
1
Inverse
Inverse
-
Inverse
-
-
-
-
PWD
X
X
X
X
X
X
X
X
I²C Table: Group Skew Control Register
Byte 18
Pin #
Name
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
CPUSkw1
CPUSkw0
Reserved
Reserved
Reserved
ASYNC3
ASYNC1
ASYNC0
Control
Function
CPU-CPU Skew
Control
Reserved
Reserved
Reserved
Async Freq Fix PLL
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
See Table 3: 4-Steps Skew
Programming Table
-
-
-
-
-
-
See Table 4: Asynchronous
Frequency Programming
Table
PWD
1
1
0
0
0
0
0
0
0731—09/18/02
10