ICS952802 Datasheet, PDF (8/19 Pages) Integrated Circuit Systems – Programmable Timing Control Hu for P4 processor

Integrated
Circuit
Systems, Inc.
ICS952802
Advance Information
I²C Table: Byte Count Register
Byte 8
Pin #
Name
Control
Function
Type
0
Bit 7
-
BC7
RW
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
BC6
Writing to this register
RW
-
BC5
will configure how
RW
-
BC4
many bytes will be read
RW
-
BC3
back, default is 0F = 15
RW
-
BC2
bytes.
RW
-
BC1
RW
-
Bit 0
-
BC0
RW
-
1
PWD
-
0
-
0
-
0
-
0
-
1
-
1
-
1
-
1
I²C Table: Watchdog Timer Register
Byte 9
Pin #
Name
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
WD7
WD6
WD5
WD4
WD3
WD2
WD1
WD0
Control
Function
These bits represent
X*290ms the watchdog
timer will wait before it
goes to alarm mode.
Default is 16 X 290ms
=4.64 seconds
Type
RW
RW
RW
RW
RW
RW
RW
RW
I²C Table: VCO Control Select Bit & WD Timer Control Register
Byte 10
Pin #
Name
Control
Function
Bit 7
-
M/NEN
M/N Programming
Enable
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
WDEN
Reserved
WD SF4
WD SF3
WD SF2
WD SF1
WD SF0
Watchdog Enable
Reserved
Writing to these bit will
configure the safe
frequency as Byte 4 bit
2, (7:4)
Type
RW
RW
RW
RW
RW
RW
RW
RW
I²C Table: VCO Frequency Control Register
Byte 11
Pin #
Name
Control
Function
Bit 7
-
N Div8
N Divider Bit 8
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
M Div6
M Div5
M Div4
M Div3
M Div2
M Div1
M Div0
The decimal
representation of M Div
(6:0) + 2 is equal to
reference divider value.
Default at power up =
latch-in or Byte 0 Rom
table.
0731—09/18/02
Type
RW
RW
RW
RW
RW
RW
RW
RW
8
0
1
PWD
-
-
0
-
-
0
-
-
0
-
-
1
-
-
0
-
-
0
-
-
0
-
-
0
0
Disable
Disable
-
-
-
-
-
-
1
Enable
Enable
-
-
-
-
-
-
PWD
0
0
0
0
0
0
0
1
0
1
PWD
-
-
X
-
-
X
-
-
X
-
-
X
-
-
X
-
-
X
-
-
X
-
-
X