ICS952802 Datasheet, PDF (3/19 Pages) Integrated Circuit Systems – Programmable Timing Control Hu for P4 processor

Integrated
Circuit
Systems, Inc.
ICS952802
Advance Information
Pin Description
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
1 VDDREF
2 _*FS0/REF0
3 **FS1/REF1
4 **FS2/REF2
5 GNDREF
6 X1
7 X2
8 GNDZ
9 ZCLK0
10 ZCLK1
11 VDDZ
12 *PCI_STOP#/PCICLK8
13 **FS3/PCICLK_F0
14 **FS4/PCICLK_F1
15 VDDPCI
16 GNDPCI
17 PCICLK0
18 PCICLK1
19 PCICLK2
20 PCICLK3
21 PCICLK4
22 PCICLK5
23 GNDPCI
24 VDDPCI
PWR
I/O
I/O
I/O
PWR
IN
OUT
PWR
OUT
OUT
PWR
I/O
I/O
I/O
PWR
PWR
OUT
OUT
OUT
OUT
OUT
OUT
PWR
PWR
Ref, XTAL power supply, nominal 3.3V
Frequency select latch input pin / 14.318 MHz reference clock.
Frequency select latch input pin / 14.318 MHz reference clock.
Frequency select latch input pin / 14.318 MHz reference clock.
Ground pin for the REF outputs.
Crystal input,nominally 14.318MHz.
Crystal output, nominally 14.318MHz.
Ground pin for the ZCLK outputs
3.3V Hyperzip clock output.
3.3V Hyperzip clock output.
Power supply for ZCLK clocks, nominal 3.3V
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input low. This
input is selected by IIC.
Frequency select latch input pin / 3.3V PCI free running clock output.
Frequency select latch input pin / 3.3V PCI free running clock output.
Power supply for PCI clocks, nominal 3.3V
Ground pin for the PCI outputs
PCI clock output.
PCI clock output.
PCI clock output.
PCI clock output.
PCI clock output.
PCI clock output.
Ground pin for the PCI outputs
Power supply for PCI clocks, nominal 3.3V
25 PCICLK6/SEL_Reset#*
I/O PCI clock output / Latch input pin to select pin 48 function; 0 = Reset#. 1 = CPU_Stop#
26 PCICLK7/12MHz/SELPCI_12#**
I/O
PCICLK/12MHz clock output / Latched select input for PCI/12MHz output. 0 = 12MHz,
1 = PCICLK.
27 SDATA
I/O Data pin for I2C circuitry 5V tolerant
28 GND48
PWR Ground pin for the 48MHz outputs
29 24_48MHz/SEL24_48#*~
I/O
24/48MHz clock output / Latched select input for 24/48MHz output. 0=48MHz, 1 =
24MHz.
30 12_48MHz/SEL12_48#**
I/O
12/48MHz clock output / Latched select input for 24/48MHz output. 0=48MHz, 1 =
12MHz.
31 AVDD48
PWR Power for 24/48MHz outputs and fixed PLL core, nominal 3.3V
32 SCLK
IN Clock pin of I2C circuitry 5V tolerant
33 VDDAGP
PWR Power supply for AGP clocks, nominal 3.3V
34 AGPCLK1
OUT AGP clock output
35 AGPCLK0
OUT AGP clock output
36 GNDAGP
PWR Ground pin for the AGP outputs
Asynchronous active low input pin used to power down the device into a low power
37 PD#*
IN state. The internal clocks are disabled and the VCO and the crystal are stopped. The
latency of the power down will not be greater than 3ms.
38 AVDD
PWR 3.3V Analog Power pin for Core PLL
39 AGND
PWR Analog Ground pin for Core PLL
40 GNDCPU
PWR Ground pin for the CPU outputs
41 CPUCLK8C0
OUT "Complementary" clocks of differential 3.3V push-pull K8 pair.
42 CPUCLK8T0
OUT "True" clocks of differential 3.3V push-pull K8 pair.
43 VDDCPU
PWR Supply for CPU clocks, 3.3V nominal
44 VDDCPU
PWR Supply for CPU clocks, 3.3V nominal
45 CPUCLK8C1
OUT "Complementary" clocks of differential 3.3V push-pull K8 pair.
46 CPUCLK8T1
OUT "True" clocks of differential 3.3V push-pull K8 pair.
47 GNDCPU
PWR Ground pin for the CPU outputs
48 CPU_STOP#/Reset#*
I/O Slectable real time CPU_Stop# (Input) or Reset# (Output)
* Internal Pull-Up Resistor ** Internal Pull-Down Resistor ~ This Output has 1.5X Drive Strength
0731—09/18/02
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