ICS951402 Datasheet, PDF (9/23 Pages) Integrated Circuit Systems – Programmable Timing Control Hub for P4 processor

Integrated
Circuit
Systems, Inc.
ICS951402
Advance Information
I²C Table: Watchdog Timer Register
Byte 9 ^{Pin #}
Name
Control Function Type 0
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
WD7
RW
-
WD6
These bits represent _RW
-
WD5
X*293ms the
RW
-
WD4
watchdog timer will
wait before it goes to
RW
-
WD3
alarm mode. Default ^RW
-
WD2
is 16 X 293ms =4.688 ^RW
-
WD1
seconds
RW
-
WD0
RW
-
1
PWD
-
0
-
0
-
0
-
1
-
0
-
0
-
0
-
0
I²C Table: WD Timer Control Register
Byte 10 ^{Pin # Name}
Control
Function
Bit 7
-
M/NEN
M/N Programming
Enable
Bit 6
-
WDEN
Watchdog Enable
Type
RW
RW
Bit 5
-
WDStatus
WD Status Control RW
Bit 4
-
WD SF4
Bit 3
-
WD SF3
Bit 2
-
WD SF2
Bit 1
-
WD SF1
Bit 0
-
WD SF0
Note: If Byte4 bit1 = 0 then FS4=0
RW
Writing to these bit will _RW
configure the safe
frequency as Byte 0 Bit
RW
(6:0)
RW
RW
0
Latched
Inputs
Disable
OFF
-
-
-
-
-
1
IIC Prog.
B (11:17)
Enable
ON
-
-
-
-
-
PWD
0
0
0
1
0
0
0
0
I²C Table: VCO Frequency Control Register
Byte 11 ^{Pin # Name}
Control
Function
Type
0
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
N Div8
N Divider Bit 8
RW
-
M Div6
The decimal
RW
-
M Div5
representation of M ^RW
-
M Div4
Div (6:0) is equal to RW
-
M Div3
reference divider RW
-
M Div2
value. Default at _RW
-
M Div1
power up = latch-in _RW
-
M Div0
or Byte 0 Rom table. _RW
-
1
PWD
-
X
-
X
-
X
-
X
-
X
-
X
-
X
-
X
0660—05/05/05
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