ICS951402 Datasheet, PDF (11/23 Pages) Integrated Circuit Systems – Programmable Timing Control Hub for P4 processor

Integrated
Circuit
Systems, Inc.
ICS951402
Advance Information
I²C Table: Output Divider Control Register
Byte 15 ^{Pin #}
Name
Control
Function
Type
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
SD Div3
SD Div2
SD Div1
SD Div0
CPU Div3
CPU Div2
CPU Div1
CPU Div0
SDRAM divider ratio ^RW
can be configured RW
via these 4 bits _RW
individually.
RW
CPU divider ratio can ^RW
be configured via RW
these 4 bits
RW
individually.
RW
0
1
See Table 2: Divider
Ratio Combination
Table
See Table 2: Divider
Ratio Combination
Table
PWD
X
X
X
X
X
X
X
X
Table 2: CPU, SDRAM, AGP and PCI66 Divider Ratio Combination Table
Divider (3:2)
Bit
00
01
10
11
MSB
1
2
4
8
00
0000
2
0100
4
1000
8
1100
16
01
0001
3
0101
6
1001
12
1101
24
10
0010
5
0110
10
1010
20
1110
40
11
0011
7
0111
14
1011
28
1111
56
LSB Address Div Address Div Address Div Address Div
Table 3: PCI33 Divider Ratio Combination Table
Divider (3:2)
Bit
00
01
10
11
MSB
1
2
4
8
00
0000
4
0100
8
1000
16
1100
32
01
0001
3
0101
6
1001
12
1101
24
10
0010
5
0110
10
1010
20
1110
40
11
0011
7
0111
14
1011
28
1111
56
LSB Address Div Address Div Address Div Address Div
0660—05/05/05
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