ICS951402 Datasheet, PDF (16/23 Pages) Integrated Circuit Systems – Programmable Timing Control Hub for P4 processor

Integrated
Circuit
Systems, Inc.
ICS951402
Advance Information
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . 4.6 V
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
T_A = 0 - 70C; Supply Voltage V_DD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN TYP
Input High Voltage
V_IH
2
Input Low Voltage
Input High Current
Input Low Current
Operating Supply Current
Powerdown Current
Input Frequency
Pin Inductance
Input Capacitance¹
Clk Stabilization^1,2
V_IL
I_IH
I_IL1
I_IL2
I_DD3.3OP
I_DD3.3OP
I_DD3.3PD
F_i
L_pin
C_IN
C_OUT
C_INX
T_STAB
V_IN = V_DD
V_IN = 0 V; Inputs with no pull-up
resistors
V_IN = 0 V; Inputs with pull-up
resistors
C_L = Full load; Select @ 100
MHz
C_L =Full load; Select @ 133
MHz
IREF=5 mA
V_DD = 3.3 V
V_SS -
0.3
-5
-5
-200
229
220
230
233
38.1
14.32
Logic Inputs
Output pin capacitance
X1 & X2 pins
27 36
From PowerUp or deassertion of
PowerDown to 1st clock.
1
MAX
V_DD
+0.3
0.8
5
360
360
45
7
5
6
45
1.8
Delay¹
t_PZH,t_PZL Output enable delay (all outputs) 1
10
t_PHZ,t_PLZ Output disable delay (all outputs) 1
10
1_{Guaranteed by design, not 100% tested in production.}
2_{See timing diagrams for buffered and un-buffered timing requirements.}
UNITS
V
V
mA
mA
mA
mA
mA
MHz
nH
pF
pF
pF
ms
ns
ns
0660—05/05/05
16