ICS951402 Datasheet, PDF (2/23 Pages) Integrated Circuit Systems – Programmable Timing Control Hub for P4 processor

Integrated
Circuit
Systems, Inc.
ICS951402
Advance Information
Pin Description
PIN NUMBER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
PIN NAME
VDDREF
FS0/REF0
FS1/REF1
FS2/REF2
GNDREF
X1
X2
GND
VDD
*VttPWR_GD/PD#
PCI66/33#_SEL
PCI_STOP#*
VDDPCI
FS3/PCICLK_F0
FS4/PCICLK_F1
PCICLK0
PCICLK1
GNDPCI
VDDPCI
PCICLK2
PCICLK3
PCICLK4
PCICLK5
GNDPCI
GND48
24_48MHz/SEL24_48#MHz**
48MHz_1
48MHz_0
AVDD48
VDDAGP
AGPCLK1
AGPCLK0
GNDAGP
SDATA
SCLK
AVDD
GND
IREF
CPUCLKC0
TYPE
PWR
I/O
I/O
I/O
PWR
IN
OUT
PWR
PWR
IN
IN
IN
PWR
I/O
I/O
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
PWR
PWR
I/O
OUT
OUT
PWR
PWR
OUT
OUT
PWR
I/O
IN
PWR
PWR
OUT
OUT
DESCRIPTION
Ref, XTAL power supply, nominal 3.3V
Frequency select latch input pin / 14.318 MHz reference clock.
Frequency select latch input pin / 14.318 MHz reference clock.
Frequency select latch input pin / 14.318 MHz reference clock.
Ground pin for the REF outputs.
Crystal input, Nominally 14.318MHz.
Crystal output, Nominally 14.318MHz
Ground pin.
Power supply, nominal 3.3V
This 3.3V LVTTL input is a level sensitive strobe used to determine
when latch inputs are valid and are ready to be sampled. This is an
active high input. / Asynchronous active low input pin used to power
down the device into a low power state.
Selects all PCI clock frequencies to be 33Mhz or 66Mhz. 0 = 33Mhz , 1
= 66Mhz
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when
input low
Power supply for PCI clocks, nominal 3.3V
Frequency select latch input pin / 3.3V PCI free running clock output.
Frequency select latch input pin / 3.3V PCI free running clock output.
PCI clock output.
PCI clock output.
Ground pin for the PCI outputs
Power supply for PCI clocks, nominal 3.3V
PCI clock output.
PCI clock output.
PCI clock output.
PCI clock output.
Ground pin for the PCI outputs
Ground pin for the 48MHz outputs
24/48MHz clock output / Latched select input for 24/48MHz output.
0=48MHz, 1 = 24MHz.
48MHz clock output.
48MHz clock output.
Analog power for 48MHz outputs and fixed PLL core, nominal 3.3V
Power supply for AGP clocks, nominal 3.3V
AGP clock output
AGP clock output
Ground pin for the AGP outputs
Data pin for SMBus circuitry, 5V tolerant.
Clock pin of SMBus circuitry, 5V tolerant.
3.3V Analog Power pin for Core PLL
Ground pin.
This pin establishes the reference current for the differential current-
mode output pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current. 475 ohms is the
standard value.
Complementary clock of differential pair CPU outputs. This clock is 180
degrees out of phase with the SDRAM clock.
40
CPUCLKT0
OUT ^{True clock of differential pair CPU outputs. This clock is in phase with}
the SDRAM clock
41
GNDCPU
PWR Ground pin for the CPU outputs
42
VDDCPU
PWR Supply for CPU clocks, 3.3V nominal
43
CPUCLKC1
OUT ^{Complementary clock of differential pair CPU outputs. This clock is 180}
degrees out of phase with the SDRAM clock.
44
CPUCLKT1
OUT
True clock of differential pair CPU outputs. This clock is in phase with
the SDRAM clock
45
CPU_STOP#*
IN Stops all CPUCLK besides the free running clocks
46
GNDSDR
PWR Ground pin for the SDRAM outputs.
47
SDRAM_OUT
OUT SDRAM seed clock output for external buffer
48
VDDSDR
PWR Supply for SDRAM clocks, nominal 3.3V.
0660—05/05/05
2