ICS950402 Datasheet, PDF (9/19 Pages) Integrated Circuit Systems – AMD - K8 System Clock Chip

ICS950402
I²C Table: VCO Frequency Control Register
Byte 12
Pin #
Name
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
N Div7
N Div6
N Div5
N Div4
N Div3
N Div2
N Div1
N Div0
Control
Function
The decimal
representation of N Div
(8:0) + 8 is equal to VCO
divider value. Default at
power up = latch-in or
Byte 0 Rom table.
I²C Table: Spread Spectrum Control Register
Byte 13
Pin #
Name
Control
Function
Bit 7
-
SSP7
Bit 6
-
SSP6
These Spread Spectrum
Bit 5
-
SSP5
bits will program the
Bit 4
-
SSP4
spread pecentage. It is
Bit 3
-
SSP3
recommended to use ICS
Bit 2
-
SSP2
Spread % table for
Bit 1
-
SSP1
spread programming.
Bit 0
-
SSP0
I²C Table: Spread Spectrum Control Register
Byte 14
Pin #
Name
Control
Function
Bit 7
-
Reserved
Reserved
Bit 6
-
Reserved
Reserved
Bit 5
-
Reserved
Reserved
Bit 4
-
SSP12
Bit 3
-
SSP11
It is recommended to use
Bit 2
-
SSP10
ICS Spread % table for
Bit 1
-
SSP9
spread programming.
Bit 0
-
SSP8
I²C Table: Output Divider Control Register
Byte 15
Pin #
Name
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
PCI / HTTDiv3
PCI / HTTDiv2
PCI / HTTDiv1
PCI / HTTDiv0
CPU Div3
CPU Div2
CPU Div1
CPU Div0
Control
Function
PCI(9:7)/HTT(2:0) divider
ratio can be configured
via these 4 bits
individually.
CPU divider ratio can be
configured via these 4
bits individually.
Type
RW
RW
RW
RW
RW
RW
RW
RW
Type
RW
RW
RW
RW
RW
RW
RW
RW
Type
R
R
R
RW
RW
RW
RW
RW
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
PWD
-
-
X
-
-
X
-
-
X
-
-
X
-
-
X
-
-
X
-
-
X
-
-
X
0
1
PWD
-
-
X
-
-
X
-
-
X
-
-
X
-
-
X
-
-
X
-
-
X
-
-
X
0
1
PWD
-
-
0
-
-
0
-
-
1
-
-
X
-
-
X
-
-
X
-
-
X
-
-
X
0
1
See Table 2: Divider Ratio
Combination Table
See Table 2: Divider Ratio
Combination Table
PWD
X
X
X
X
X
X
X
X
0700B—04/30/04
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