ICS950402 Datasheet, PDF (10/19 Pages) Integrated Circuit Systems – AMD - K8 System Clock Chip

ICS950402
I²C Table: Output Divider Control Register
Byte 16
Pin #
Name
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
Reserved
Reserved
Reserved
Reserved
PCIDiv3
PCIDiv2
PCIDiv1
PCIDiv0
Control
Function
Reserved
Reserved
Reserved
Reserved
PCI divider ratio can be
configured via these 4
bits individually.
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
-
-
-
-
-
-
-
-
See Table 2: Divider Ratio
Combination Table
PWD
X
X
X
X
X
X
X
X
Table 2: CPU, HTT & PCI Divider Ratio Combination Table
Bit
00
01
10
11
LSB
00
0000
0001
0010
0011
Address
Divider (3:2)
01
10
11
MSB
8
0100
4
1000
8
1100
4
12
0101
6
1001
12
1101
6
20
0110
10
1010
20
1110
10
28
0111
14
1011
28
1111
14
Div
Address
Div
Address
Div
Address
Div
I²C Table: Output Divider Control Register
Byte 17
Pin #
Name
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
Reserved
Reserved
HTTINV
CPUINV
PCI DIV3
PCI DIV2
PCI DIV1
PCI DIV0
Control
Function
Reserved
Reserved
HTT Phase Invert
CPU Phase Invert
PCI10/HTTCLK3 divider
ratio can be configured
via these 4 bits
I²C Table: Group Skew Control Register
Byte 18
Pin #
Name
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Control
Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Type
RW
RW
RW
RW
RW
RW
RW
RW
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
-
-
Default
Default
1
-
-
Inverse
Inverse
See Table 2: Divider Ratio
Combination Table
PWD
X
X
X
X
X
X
X
X
0
1
PWD
-
-
X
-
-
X
-
-
X
-
-
X
-
-
X
-
-
X
-
-
X
-
-
X
0700B—04/30/04
10