ICS950402 Datasheet, PDF (8/19 Pages) Integrated Circuit Systems – AMD - K8 System Clock Chip

ICS950402
I²C Table: Output Control Register
Byte 8
Pin #
Name
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Control
Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
I²C Table: Watchdog Timer Register
Byte 9
Pin #
Name
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
WD7
WD6
WD5
WD4
WD3
WD2
WD1
WD0
Control
Function
These bits represent
X*290ms the watchdog
timer will wait before it
goes to alarm mode.
Default is 16 X 290ms
=4.64 seconds
I²C Table: VCO Control Select Bit & WD Timer Control Register
Byte 10
Pin #
Name
Control
Function
Bit 7
-
M/NEN
M/N Programming
Enable
Bit 6
-
Bit 7
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
WDEN
WDRB
WD SF4
WD SF3
WD SF2
WD SF1
WD SF0
Watchdog Enable
WD Alarm Status Bit
Writing to these bit will
configure the safe
frequency as Byte0 bit
(5:1)
I²C Table: VCO Frequency Control Register
Byte 11
Pin #
Name
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
N Div8
M Div6
M Div5
M Div4
M Div3
M Div2
M Div1
M Div0
Control
Function
N Divider Bit 8
The decimal
representation of M Div
(6:0) + 2 is equal to
reference divider value.
Default at power up =
latch-in or Byte 0 Rom
table.
Type
RW
RW
RW
RW
RW
RW
RW
RW
Type
RW
RW
RW
RW
RW
RW
RW
RW
Type
RW
RW
R
RW
RW
RW
RW
RW
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
PWD
-
-
0
-
-
0
-
-
0
-
-
0
-
-
0
-
-
0
-
-
0
-
-
0
0
1
PWD
-
-
0
-
-
0
-
-
0
-
-
1
-
-
0
-
-
0
-
-
0
-
-
0
0
Disable
Disable
Normal
-
-
-
-
-
1
Enable
Enable
Alarm
-
-
-
-
-
PWD
0
0
X
0
0
0
0
1
0
1
PWD
-
-
X
-
-
X
-
-
X
-
-
X
-
-
X
-
-
X
-
-
X
-
-
X
0700B—04/30/04
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