ICS950402 Datasheet, PDF (7/19 Pages) Integrated Circuit Systems – AMD - K8 System Clock Chip

ICS950402
I²C Table: Read back and Output Control Register
Byte 4
Pin #
Name
Control
Function
Bit 7
23
PCICLK_F
Output Control
Bit 6
12
PCICLK11
Output Control
Bit 5
-
24_48SEL
-
Bit 4
-
FS3
-
Bit 3
-
FS2
-
Bit 2
-
FS1
-
Bit 1
-
FS0
-
Bit 0
11
PCICLK10/HTTCLK3
Output Control
Type
RW
RW
R
R
R
R
R
RW
I²C Table: Vendor and Revision ID Register
Byte 5
Pin #
Name
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Control
Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
I²C Table: Byte Count Register
Byte 6
Pin #
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
Name
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
Control
Function
Writing to this register will
configure how many
bytes will be read back,
default is 0F = 15 bytes.
I²C Table: Output Control Register
Byte 7
Pin #
Name
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
RID3
RID2
RID1
RID0
VID3
VID2
VID1
VID0
Control
Function
REVISION ID
VENDOR ID
Type
RW
RW
RW
RW
RW
RW
RW
RW
Type
RW
RW
RW
RW
RW
RW
RW
RW
Type
R
R
R
R
R
R
R
R
0
Disable
Disable
-
-
-
-
-
Disable
1
Enable
Enable
-
-
-
-
-
Enable
PWD
1
1
1
1
1
1
1
1
0
1
PWD
-
-
0
-
-
0
-
-
0
-
-
0
-
-
0
-
-
0
-
-
0
-
-
1
0
1
PWD
-
-
0
-
-
0
-
-
0
-
-
0
-
-
1
-
-
1
-
-
1
-
-
1
0
1
PWD
-
-
0
-
-
0
-
-
0
-
-
0
-
-
0
-
-
0
-
-
0
-
-
1
0700B—04/30/04
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