ICS87993I Datasheet, PDF (9/16 Pages) Integrated Circuit Systems – 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH

Integrated
Circuit
Systems, Inc.
ICS87993I
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH
SCHEMATIC EXAMPLE
Figure 5A shows a schematic example of the ICS87993I. In this
example, the CLK0/nCLK0 input is selected as primary. The in-
put is driven by an LVPECL driver. Feedback can be either from
Bank A or Bank B depending on the application. The decoupling
capacitors should be physically located near the power pin.
For ICS87993I, the unused outputs can be left floating.
VC C
LVCMOS
VC C
Zo = 50 Ohm
Zo = 50 Ohm
LVPECL Driv er
R9
50
C7 (Option)
0.1u
VCC
VCC
R 16
1K
R7
10
VCC A
R15
1K
C16
10u
C11
0. 01u
U1
R2
1K
R 10
50
R 11
50
C LK_SEL
1
2 ^nMR
3
4
nALM_R S
C LK0
5 ^nCLK0
6 ^CLK_SEL
7
8
C LK1
nCLK1
VEE
ICS87993I
VCC
24
VCC ₂₃
QB0
nQB0
22
21
QB1 ₂₀
nQB1 ₁₉
QB2
nQB2
VCC
18
17
Zo = 50
Zo = 50
+
-
R2
R1
50
50
C5 (Option)
R3
0.1u
50
VCC
Zo = 50 Ohm
Zo = 50 Ohm
LVPECL Driv er
R 12
50
C6 (Option)
0.1u
LVCMOS
R5
R4
50
50
R13
50
C8 (Option)
0. 1u
R14
50
R6
50
(U1-16)
VCC
C1
0.1uF
LVCMOS
(U1-17) (U1-24) (U1-29)
C2
0. 1uF
C3
0.1uF
C4
0. 1uF
LVCMOS
FIGURE 5A. ICS87993I LVPECL SCHEMATIC EXAMPLE
87993AYI
www.icst.com/products/hiperclocks.html
9
REV. B May 21, 2003