ICS87993I Datasheet, PDF (7/16 Pages) Integrated Circuit Systems – 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH

Integrated
Circuit
Systems, Inc.
ICS87993I
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 3 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V_CC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V = 3.3V, V_REF should be 1.25V
CC
and R2/R1 = 0.609.
VCC
Single Ended Clock Input
V_REF
C1
0.1u
R1
1K
CLKx
nCLKx
R2
1K
FIGURE 3. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
87993AYI
www.icst.com/products/hiperclocks.html
7
REV. B May 21, 2003