ICS87993I Datasheet, PDF (4/16 Pages) Integrated Circuit Systems – 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH

Integrated
Circuit
Systems, Inc.
ICS87993I
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH
TABLE 3D. LVPECL DC CHARACTERISTICS, V_CC = V_CCA = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
V_OH
Output High Voltage; NOTE 1
V_OL
Output Low Voltage; NOTE 1
V_SWING Peak-to-Peak Output Voltage Swing
NOTE
1:
Outputs
terminated
with
50Ω
to
V
CC
-
2V.
V_CC - 1.4
V_CC - 2.0
0.6
V_CC - 1.0
V
V_CC - 1.7
V
1.0
V
TABLE
4. AC
CHARACTERISTICS,
V
CC
=
V
CCA
=
3.3V±5%,
TA
=
-40°C
TO
85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
f_VCO
PLL VCO Lock Range
t_PWI
CLKx to Q
t_PD
Propagation Delay _{CLKx to EXT_FB;}
NOTE 2
t_{R /} t_F
tsk(o)
Output Rise Time
Output Skew;
NOTE 3
∆_PER/CYCLE
Rate of change
of Periods
odc
Output Duty Cycle
Within Bank
All Outputs
75MHz Output;
NOTE 1, 4
150MHz Output;
NOTE 1, 4
75MHz Output;
NOTE 1, 5
150MHz Output;
NOTE 1, 5
PLL_SEL = LOW
PLL_SEL = HIGH
fVCO ≤ 360MHz
PLL_SEL = HIGH
fVCO ≤ 500MHz
20% to 80% @ 50MHz
Tested at
typical conditions
f ≤ 360MHz
200
25
2.8
-150
-150
200
45
3.45
0
0
20
10
200
100
500
MHz
75
%
4.1
ns
170
ps
200
ps
800
ps
70
ps
100
ps
50
ps/cycle
25
ps/cycle
400 ps/cycle
200 ps/cycle
55
%
tjit(cc)
Cycle-to-Cycle Jitter (RMS); NOTE 1
20
ps
t_L
PLL Lock Time; NOTE 1
10
ms
All parameters measured at f_MAX unless noted otherwise.
NOTE 1: These parameters are guaranteed by characterization. Not tested in production.
NOTE 2: Defined as the time difference between the input reference clock and the averaged feedback input signal,
when the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 4: Specification holds for a clock switch between two signals no greater than 400ps out of phase.
Delta period change per cycle is averaged over the clock switch excursion.
NOTE 5: Specification holds for a clock switch between two signals no greater than ±π out of phase.
Delta period change per cycle is averaged over the clock switch excursion.
87993AYI
www.icst.com/products/hiperclocks.html
4
REV. B May 21, 2003