ICS87993I Datasheet, PDF (2/16 Pages) Integrated Circuit Systems – 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH

Integrated
Circuit
Systems, Inc.
ICS87993I
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH
TABLE 1. PIN DESCRIPTIONS
Number
1
2
3
4
5
6
7
8, 9, 12
10
Name
nMR
nALARM_RESET
CLK0
nCLK0
SEL_CLK
CLK1
nCLK1
V_EE
EXT_FB
Type
Description
Input
Input
Pullup
Pullup
Active LOW Master Reset. When logic LOW, the internal dividers are
reset causing the true outputs Qx to go low and the inverted outputs
nQx to go high. When logic HIGH, the internal dividers and the outputs
are enabled. LVCMOS / LVTTL interface levels.
When LOW, resets the input bad flags and aligns CLK_SELECTED
with SEL_CLK. LVCMOS / LVTTL interface levels.
Input Pulldown Non-inverting differential clock input.
Input Pullup Inverting differential clock input.
Input
Pulldown
Clock select input. When LOW, selects CLK0, nCLK0 inputs. When
HIGH, selects CLK1, nCLK1 inputs. LVCMOS / LVTTL interface levels.
Input Pulldown Non-inverting differential clock input.
Input Pullup Inverting differential clock input.
Power
Negative supply pins.
Input Pulldown Differential external feedback.
11
13
14
15
16, 17,
24, 29
18, 19
nEXT_FB
Input
CLK_SELECTED Output
INP1BAD
Output
INP0BAD
V_CC
nQB2, QB2
Output
Power
Output
Pullup
Differential external feedback.
LOW, when CLK0, nCLK0 is selected, HIGH, when CLK1, nCLK1
is selected. LVCMOS / LVTTL interface levels.
Indicates detection of a bad input reference clock 1 with respect to the
feedback signal. The output is active HIGH and will remain HIGH until
the alarm reset is asserted.
Indicates detection of a bad input reference clock 0 with respect to the
feedback signal. The output is active HIGH and will remain HIGH until
the alarm reset is asserted.
Core supply pins.
Differential output pair. LVPECL interface levels.
20, 21
nQB1, QB1 Output
Differential output pair. LVPECL interface levels.
22, 23
nQB0, QB0 Output
Differential output pair. LVPECL interface levels.
25, 26
nQA1, QA1 Output
Differential output pair. LVPECL interface levels.
27, 28
nQA0, QA0 Output
Differential output pair. LVPECL interface levels.
30
V_CCA
Power
Analog supply pin.
31
MAN_OVERRIDE
Input
Pulldown
Manual override. When HIGH, disables internal clock switch circuitry.
LVCMOS / LVTTL interface levels.
Selects between the PLL and reference clock as the input to the
32
PLL_SEL
Input Pullup dividers. When LOW, selects reference clock.When HIGH, selects PLL.
LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C_IN
R_PULLUP
R_PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
KΩ
KΩ
87993AYI
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2
REV. B May 21, 2003