ICS87993I Datasheet, PDF (1/16 Pages) Integrated Circuit Systems – 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH

Integrated
Circuit
Systems, Inc.
ICS87993I
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH
GENERAL DESCRIPTION
The ICS87993I is a PLL clock driver designed
,&6
specifically for redundant clock tree designs. The
HiPerClockS™ _{device receives two differential LVPECL clock}
signals from which it generates 5 new differen-
tial LVPECL clock outputs. Two of the output pairs
regenerate the input signal frequency and phase while the
other three pairs generate 2x, phase aligned clock outputs.
External PLL feedback is used to also provide zero delay
buffer performance.
FEATURES
• 5 differential 3.3V LVPECL outputs
• Selectable differential clock inputs
• CLKx, nCLKx pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• VCO range: 200MHz to 500MHz
• External feedback for “zero delay” clock regeneration
with configurable frequencies
The ICS87993I Dynamic Clock Switch (DCS) circuit continu-
ously monitors both input CLK signals. Upon detection of a
failure (CLK stuck HIGH or LOW for at least 1 period), the
INP_BAD for that CLK will be latched (H). If that CLK is the
primary clock, the DCS will switch to the good secondary
clock and phase/frequency alignment will occur with minimal
output phase disturbance. The typical phase bump caused
by a failed clock is eliminated.
• Cycle-to-cycle jitter (RMS): 20ps (maximum)
• Output skew: 70ps (maximum), within one bank
• 3.3V supply voltage
• -40°C to 85°C ambient operating temperature
• Pin compatible with MPC993
PIN ASSIGNMENT
BLOCK DIAGRAM
PLL_SEL
CLK_SELECTED
INP1BAD
INP0BAD
MAN_OVERRIDE
ALARM_RESET
Dynamic Switch
Logic
87993AYI
SEL_CLK
nCLK0
CLK0
nCLK1
CLK1
nEXT_FB
EXT_FB
nMR
nQA1
QA1
nQA0
QA0
VCC
VCCA
MAN_OVERRIDE
PLL_SEL
24 23 22 21 20 19 18 17
25
16
26 _ICS87993I 15
27
14
28 ^{32-Lead QFP (LQFP)} 13
7mm x 7mm x 1.4mm
29
package body
12
30
Y Package
11
31
Top View
10
32
9
12345678
VCC
INP0BAD
INP1BAD
CLK_SELECTED
VEE
nEXT_FB
EXT_FB
VEE
÷2
PLL
÷4
www.icst.com/products/hiperclocks.html
1
nQB0
QB0
nQB1
QB1
nQB2
QB2
nQA0
QA0
nQA1
QA1
REV. B May 21, 2003