ICS8624 Datasheet, PDF (9/16 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER

Integrated
Circuit
Systems, Inc.
ICS8624
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER
LAYOUT GUIDELINE
The schematic of the ICS8624 layout example is shown in
Figure 4A. The ICS8624 recommended PCB board layout for
this example is shown in Figure 4B. This layout example is
used as a general guideline. The layout in the actual system
will depend on the selected component types, the density of
the components, the density of the traces, and the stack up
of the P.C. board.
VDD
SP = Space (i.e. not intstalled)
VDDA
R7
VDD
RU2 RU3 RU4 RU5
SP
1K
1K
SP
10
VDD=3.3V
C11
0.01u
C16
CLK_SEL
VDDO=1.8V
10u
PLL_SEL
SEL0
SEL1
DIV_SEL[1:0] = 01
155.5 MHz
Zo = 50 Ohm
+
RD2
1K
RD3
SP
RD4
SP
RD5
1K
VDD
VDDO
Zo = 50 Ohm
-
LVHSTL_input
3.3V
(155.5 MHz)
SEL0
Zo = 50 Ohm
SEL1
Zo = 50 Ohm
3.3V PECL Driver
CLK_SEL
R8
R9
50
50
U1
1
2
3
4
5
6
7
SEL0
SEL1
CLK0
nCLK0
CLK1
nCLK2
8
CLK_SEL
MR
8624
VDDO
Q3
nQ3
Q2
nQ2
Q1
24
23
22
21
20
19
18
nQ1
VDDO
17
R4A R4B
50
50
Bypass capacitor located near the power pins
(U1-9) VDD (U1-32)
C1
0.1uF
C6
0.1uF
R10
(U1-16) VDDO (U1-17) (U1-24) (U1-25)
50
R2B
R2A
50
50
C2
0.1uF
C4
0.1uF
C5
0.1uF
C7
0.1uF
FIGURE 4A. ICS8624 HSTL ZERO DELAY BUFFER SCHEMATIC EXAMPLE
8624BY
www.icst.com/products/hiperclocks.html
9
REV. C JUNE 15, 2004