ICS8624 Datasheet, PDF (1/16 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER

Integrated
Circuit
Systems, Inc.
ICS8624
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER
GENERAL DESCRIPTION
ICS
The ICS8624 is a high performance, 1-to-5
Differential-to-HSTL zero delay buffer and
HiPerClockS™ _{a member of the HiPerClockS™ family of High}
Performance Clock Solutions from ICS. The
ICS8624 has two selectable clock input pairs.
The CLK0, nCLK0 and CLK1, nCLK1 pair can accept most
standard differential input levels. The VCO operates at a fre-
quency range of 250MHz to 700MHz. Utilizing one of the
outputs as feedback to the PLL, output frequencies up to
700MHz can be regenerated with zero delay with respect to
the input. Dual reference clock inputs support redundant clock
or multiple reference applications.
FEATURES
• Fully integrated PLL
• 5 differential HSTL outputs
• Selectable differential CLKx, nCLKx input pairs
• CLKx, nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, HSTL, SSTL, HCSL
• Output frequency range: 31.25MHz to 700MHz
• Input frequency range: 31.25MHz to 700MHz
• VCO range: 250MHz to 700MHz
• External feedback for “zero delay” clock regeneration
• Cycle-to-cycle jitter: 25ps (maximum)
• Output skew: 25ps (maximum)
• Static phase offset: ±100ps
• 3.3V core, 1.8V output operating supply
• 0°C to 70°C ambient operating temperature
• Lead-Free package available
• Industrial temperature information available upon request
BLOCK DIAGRAM
PLL_SEL
CLK0
nCLK0
0
CLK1
1
nCLK1
CLK_SEL
FB_IN
nFB_IN
÷4, ÷8
0
1
PLL
SEL0
SEL1
MR
PIN ASSIGNMENT
Q0
nQ0
Q1
nQ1
Q2
nQ2
SEL0
32 31 30 29 28 27 26 25
1
24
VDDO
Q3
nQ3
SEL1 2
CLK0 3
23 Q3
22 nQ3
Q4
nQ4
nCLK0 4
CLK1 5
ICS8624
21 Q2
20 nQ2
nCLK1 6
19 Q1
CLK_SEL 7
18 nQ1
MR 8
1 7 VDDO
9 10 11 12 13 14 15 16
32-Lead LQFP
7mm x 7mm x 1.4mm body package
Y Package
Top View
8624BY
www.icst.com/products/hiperclocks.html
1
REV. C JUNE 15, 2004