ICS8624 Datasheet, PDF (6/16 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER

Integrated
Circuit
Systems, Inc.
ICS8624
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER
PARAMETER MEASUREMENT INFORMATION
3.3V±5% or 10%
1.8V±0.2V
VDD^,
VDDA _VDDO
HSTL
GND
SCOPE
Qx
nQx
V
DD
nCLK0,
nCLK1
V
PP
CLK0,
CLK1
Cross Points
0V
3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
GND
DIFFERENTIAL INPUT LEVEL
V
CMR
nQx
nQ
nQy
Qy
t sk(o)
nQx
Qx
tcycle n
➤
tcycle n+1
➤
t jit(cc) = tcycle n –tcycle n+1
1000 Cycles
OUTPUT SKEW
nCLK0,
nCLK1
V_OH
CLK0,
CLK1
V_OL
nFB_IN
V_OH
FB_IN
V_OL
➤ t (Ø)
tjit(Ø) = t(Ø) — t(Ø) mean = Phase Jitter
t(Ø) mean = Static Phase Offset
(where t(Ø) is any random sample, and t(Ø) mean is the average
of the sampled cycles measured on controlled edges)
PHASE JITTER AND STATIC PHASE OFFSET
CYCLE-TO-CYCLE JITTER
Clock
20%
Outputs
80%
t_R
OUTPUT RISE/FALL TIME
nQ0:nQ4
Q0:Q4
V_DDO
2
V_DDO
2
Pulse Width
t _PERIOD
V_DDO
2
nCLK0,
nCLK1
CLK0,
CLK1
nQ0:nQ4
Q0:Q4
t_PD
OUTPUT PULSE WIDTH/PERIOD
8624BY
PROPAGATION DELAY
www.icst.com/products/hiperclocks.html
6
80%
t_F
V_OD
20%
REV. C JUNE 15, 2004