ICS8624 Datasheet, PDF (2/16 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER

Integrated
Circuit
Systems, Inc.
ICS8624
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
SEL0
Input
Pulldown
Determines the input and output frequency range noted in Table 3.
LVCMOS / LVTTL interface levels.
2
SEL1
Input
Pulldown
Determines the input and output frequency range noted in Table 3.
LVCMOS / LVTTL interface levels.
3
CLK0
Input Pulldown Non-inverting differential clock input.
4
nCLK0
Input Pullup Inverting differential clock input.
5
CLK1
Input Pulldown Non-inverting differential clock input.
6
nCLK1
Input Pullup Inverting differential clock input.
7
CLK_SEL
Input
Pulldown
Clock select input. When LOW, selects CLK0, nCLK0. When HIGH, selects
CLK1, nCLK1 inputs. LVCMOS / LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
8
MR
Input
Pulldown
reset causing the true outputs Qx to go low and the inverted outputs nQx
to go high. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS / LVTTL interface levels.
9, 32
10
V_DD
nFB_IN
Power
Input
Core supply pins.
Pullup Feedback input to phase detector for regenerating clocks with "zero delay".
11
FB_IN
Input Pulldown Feedback input to phase detector for regenerating clocks with "zero delay".
12, 13
28, 29
14, 15
16, 17,
24, 25
18, 19
20, 21
22, 23
26, 27
GND
nQ0, Q0
V_DDO
nQ1, Q1
nQ2, Q2
nQ3, Q3
nQ4, Q4
Power
Output
Power
Output
Output
Output
Output
Power supply ground.
Differential clock outputs. 50Ω typical output impedance.
HSTL interface levels.
Output supply pins.
Differential clock outputs. 50Ω typical output impedance.
HSTL interface levels.
Differential clock outputs. 50Ω typical output impedance.
HSTL interface levels.
Differential clock outputs. 50Ω typical output impedance.
HSTL interface levels.
Differential clock outputs. 50Ω typical output impedance.
HSTL interface levels.
30
V_DDA
Power
Analog supply pin.
Selects between the PLL and clock as the input to the dividers.
31
PLL_SEL Input Pullup When HIGH, selects PLL. When LOW, selects reference clock.
LVCMOS / LVTTL interface levels.
NOTE 1: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
8624BY
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2
REV. C JUNE 15, 2004