ICS8624 Datasheet, PDF (5/16 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER

Integrated
Circuit
Systems, Inc.
ICS8624
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER
TABLE 4D. HSTL DC CHARACTERISTICS, V_DD = V_DDA = 3.3V±5%, V_DDO = 1.8V±0.2V, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical
V_OH
Output High Voltage; NOTE 1
1.0
V_OL
Output Low Voltage; NOTE 1
0
V_OX
Output Crossover Voltage; NOTE 2
40
V_SWING Peak-to-Peak Output Voltage Swing
0.6
NOTE 1: Outputs terminated with 50Ω to ground.
NOTE 2: Defined with respect to output voltage swing at a given condition.
Maximum
1.4
0.4
60
1.1
Units
V
V
%
V
TABLE
5.
INPUT
FREQUENCY
CHARACTERISTICS,
V
DD
=
V
DDA
=
3.3V±5%,
V
DDO
=
1.8V±0.2V,
TA
=
0°C
TO
70°C
Symbol
f_IN
Parameter
Input Frequency
CLK0, nCLK0,
CLK1, nCLK1
Test Conditions
PLL_SEL = 1
PLL_SEL = 0
Minimum
31.25
Typical
Maximum
700
700
Units
MHz
MHz
TABLE 6A. AC CHARACTERISTICS, V_DD = V_DDA = 3.3V±5%, V_DDO = 1.8V±0.2V, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
f_MAX
Output Frequency
t_PD
Propagation Delay; NOTE 1
t(Ø)
Static Phase Offset; NOTE 2, 5
IJ 700MHz
PLL_SEL = 3.3V
700
3.4
3.9
4.4
-100
100
tsk(o) Output Skew; NOTE 3, 5
25
tjit(cc) Cycle-to-Cycle Jitter; NOTE 5, 6
25
tjit(Ø) Phase Jitter; NOTE 4, 5, 6
±50
t
PLL Lock Time
1
L
t_R
Output Rise Time
20% to 80% @ 50MHz
300
700
t_F
Output Fall Time
20% to 80% @ 50MHz
300
700
t_PW
Output Pulse Width
tcycle/2 - 85 tcycle/2 tcycle/2 + 85
All parameters measured at f unless noted otherwise.
MAX
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as the time difference between the input reference clock and the averaged feedback input signal
across all conditions, when the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at output differential cross points.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Characterized at VCO frequency of 622MHz.
Units
MHz
ns
ps
ps
ps
ps
ms
ps
ps
ps
TABLE 6B. AC CHARACTERISTICS, V_DD = V_DDA = 3.3V±10%, V_DDO = 1.8V±0.2V, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical
tjit(cc) Cycle-to-Cycle Jitter; NOTE 1
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
Maximum
35
Units
ps
8624BY
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5
REV. C JUNE 15, 2004