ICS8624 Datasheet, PDF (16/16 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER

Integrated
Circuit
Systems, Inc.
ICS8624
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER
Rev Table
A
A
A
T1
T4A
B
T4C
T2
C
T4D
T6B
C
T10
REVISION HISTORY SHEET
Page
8
10
1
7-8
11 - 12
2
4
4
9
3
4
5
5
8
14
Description of Change
Switched labels on Figure 8, odc & t_PERIOD diagram.
Revised label on Figure 11 to read ICS8624 LVHSTL... from ICS8634 LVDS...
Revised Block Diagram
Updated Phase Jitter Diagram and Output Rise & Fall Time Diagram.
Revised Figures 3A & 3B.
Pin Description table - revised MR & V_DD descriptions.
Power Supply table - revised V_DD parameter description to correspond with the
Pin Description table.
Differential DC Charc. table - changed V_PP limit from 0.15V minimum to 0.1V
minimum.
Revised Single Ended Signal diagram.
Updated format.
Pin Characteristics Table - changed C_IN 4pF max. to 4pF typical.
Absolute Maximum Ratings - updated Output rating.
HSTL DC Characteristics Table - changed V_OX to 40% min. - 60% max. and
added note.
Added Table 6B AC Characteristics Table with V_DD = V_DDA = 3.3V±10%.
Changed LVHSTL to HSTL throughout the data sheet.
Added Differential Clock Input Interface section.
Added "Lead Free" part number to Ordering Information table.
Date
10/30/01
10/31/01
8/13/02
2/12/03
2/19/04
6/15/04
8624BY
www.icst.com/products/hiperclocks.html
16
REV. C JUNE 15, 2004