ICS950211 Datasheet, PDF (7/21 Pages) Integrated Circuit Systems – Programmable Timing Control Hub for P4

Integrated
Circuit
Systems, Inc.
ICS950211
Asynchronous Frequency Control Table
Byte 4 Byte 3
Bit 7 Bit 4
3V66 [0:3]
0
0
66.01 MHz
0
1
75.44 MHz
1
0
66.66 MHz
1
1
88.01 MHz
PCI_F [1:2]
PCICK [0:6]
33.005 MHz
37.72 MHz
33.33 MHz
44.005 MHz
Note
From Fix PLL (no
spread)
From Fix PLL (no
spread)
From main PLL
(Default)
From Fix PLL (no
spread)
Byte 5: Programming Edge Rate
(1 = enable, 0 = disable)
Bit Pin# PWD
Description
Bit 7
X
1 CPUCLK T/C0 Free Running Control, 0=Free Running; 1=Stoppable*
Bit 6
X
1 CPUCLK T/C1 Free Running Control, 0=Free Running; 1=Stoppable*
Bit 5
X
1 CPUCLK T/C2 Free Running Control, 0=Free Running; 1=Stoppable*
Bit 4
X
1 (Reserved)
Bit 3
X
1 (Reserved)
Bit 2
X
1 (Reserved)
Bit 1
X
1 (Reserved)
Bit 0
X
1 (Reserved)
* This functionality is only available in BF version.
Byte 6: Vendor ID Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Revision ID Bit3
Revision ID Bit2
Revision ID Bit1
Revision ID Bit0
Vendor ID Bit3
Vendor ID Bit2
Vendor ID Bit1
Vendor ID Bit0
PWD
X
X
X
X
0
0
0
1
Description
Revision ID values will be based on individual device's revision
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Byte 7: Revision ID and Device ID Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Device ID7
Device ID6
Device ID5
Device ID4
Device ID3
Device ID2
Device ID1
Device ID0
PWD
0
0
0
0
0
0
0
1
Description
Device ID values will be based on individual device
"01H" in this case.
0465E—05/17/05
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