ICS950211 Datasheet, PDF (1/21 Pages) Integrated Circuit Systems – Programmable Timing Control Hub for P4

Integrated
Circuit
Systems, Inc.
ICS950211
Programmable Timing Control Hub™ for P4™
Recommended Application:
Brookdale and Brookdale -G chipset with P4 processor.
Output Features:
• 3 - Pairs of differential CPU clocks (differential current mode)
• 5 - 3V66 @ 3.3V
• 10 - PCI @ 3.3V
• 2 - 48MHz @ 3.3V fixed
• 1 - REF @ 3.3V, 14.318MHz
• 1 - VCH/3V66 @ 3.3V, 48 MHz or 66.6 MHz
Features/Benefits:
• Programmable output frequency.
• Programmable output divider ratios.
• Programmable output rise/fall time.
• Programmable output skew.
• Programmable spread percentage for EMI control.
• Watchdog timer technology to reset system
if system malfunctions.
• Programmable watch dog safe frequency.
• Support I²C Index read/write and block read/write operations.
• Uses external 14.318MHz crystal.
Key Specifications:
• CPU Output Jitter <150ps
• 3V66 Output Jitter <250ps
• CPU Output Skew <100ps
Pin Configuration
VDDREF 1
X1 2
X2 3
GND 4
1_{PCICLK_F0}
5
1_{PCICLK_F1}
6
PCICLK_F2 7
VDDPCI 8
GND 9
1_{*WDEN/PCICLK0 10}
PCICLK1 11
PCICLK2 12
PCICLK3 13
VDDPCI 14
GND 15
PCICLK4 16
PCICLK5 17
PCICLK6 18
VDD3V66 19
GND 20
3V66_2 21
3V66_3 22
3V66_4 23
3V66_5 24
*PD# 25
VDDA 26
GND 27
*Vtt_PWRGD# 28
56 REF¹
55 FS1
54 FS0
53 CPU_STOP#*
52 CPUCLKT0
51 CPUCLKC0
50 VDDCPU
49 CPUCLKT1
48 CPUCLKC1
47 GND
46 VDDCPU
45 CPUCLKT2
44 CPUCLKC2
43 MULTSEL0*
42 I REF
41 GND
40 FS2
39 48MHz_USB/FS3**
38 48MHz_DOT
37 AVDD48
36 GND
35 3V66_1/VCH_CLK/FS4**
34 PCI_STOP#*
33 3V66_0
32 VDD
31 GND
30 SCLK
29 SDATA
56-Pin 300-mil SSOP & 240-mil TSSOP
1. These outputs have 2X drive strength.
* Internal Pull-up resistor of 120K to VDD
** these inputs have 120K internal pull-down
to GND
Block Diagram
Frequency Table
PLL2
X1
XTAL
X2
OSC
WDEN
PD#
CPU_STOP#
PCI_STOP#
MULTSEL0
FS (4:0)
SDATA
SCLK
Vtt_PWRGD#
PLL1
Spread
Spectrum
Control
Logic
Config.
Reg.
0465E—05/17/05
CPU
DIVDER
Stop
PCI
DIVDER
Stop
3V66
DIVDER
48MHz_USB
48MHz_DOT
3V66_1/VCH_CLK
REF
3 ^{CPUCLKT (2:0)}
3 ^{CPUCLKC (2:0)}
PCICLK (6:0)
7
PCICLK_F (2:0)
3
3V66 (5:2, 0)
5
I REF
FS4
FS3
FS2
FS1
FS0
CPUCLK
MHz
3V66
MHz
PCICLK
MHz
0 0 0 0 0 66.66* 66.66 33.33
0 0 0 0 1 100.00 66.66 33.33
0 0 0 1 0 200.00 66.66 33.33
0 0 0 1 1 133.33 66.66 33.33
0 0 1 0 0 100.90 67.27 33.63
0 0 1 0 1 105.00 70.00 35.00
0 0 1 1 0 109.00 72.67 36.33
0 0 1 1 1 114.00 76.00 38.00
0 1 0 0 0 117.00 78.00 39.00
0 1 0 0 1 127.00 72.86 36.43
0 1 0 1 0 130.00 74.29 37.14
0 1 0 1 1 132.50 75.71 37.89
0 1 1 0 0 205.00 70.00 35.00
0 1 1 0 1 170.00 56.67 28.33
0 1 1 1 0 180.00 60.00 30.00
0 1 1 1 1 190.00 63.33 31.67
For additional frequency selections please refer to Byte 0.
* For 950211BF version, this frequency is 166.66MHz.
Power Groups
VDDA = Analog Core PLL
VDDREF = REF, Xtal
AVDD48 = 48MHz