ICS950211 Datasheet, PDF (2/21 Pages) Integrated Circuit Systems – Programmable Timing Control Hub for P4

Integrated
Circuit
Systems, Inc.
ICS950211
General Description
The ICS950211 is a single chip clock solution for desktop designs using the Intel Brookdale chipset with PC133 or DDR
memory. It provides all necessary clock signals for such a system.
The ICS950211 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). This part
incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a
serially programmable I²C interface, this device can adjust the output clocks by configuring the frequency setting, the output
divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each
individual output clock. M/N control can configure output frequency with resolution up to 0.1MHz increment.
Pin Description
PIN NUMBER
1, 8, 14, 19,
32, 46, 50
2
PIN NAME
VDD
X1
3
X2
4, 9, 15, 20, 27, 31,
36, 41, 47
GND
24, 23, 22, 21, 33 3V66 (5:2, 0)
7,6,5
PCICLK_F(2:0)
WDEN
10
PCICLK0
18, 17, 16, 13, 12, 11 PCICLK (6:1)
25
PD#
26
VDDA
28
Vtt_PWRGD#
30
SCLK
29
SDATA
34
PCI_STOP#
35
3V66_1/VCH_CLK
FS4
37
AVDD48
38
48MHz_DOT
39
FS3
48MHz_USB
42
I REF
43
44, 48, 51
MULTSEL0
CPUCLKC (2:0)
45, 49, 52
40, 55, 54
53
56
CPUCLKT (2:0)
FS (2:0)
CPU_STOP#
REF
TYPE
DESCRIPTION
PWR 3.3V power supply.
IN Crystal input, has internal load cap (33pF) and feedback resistor from X2.
OUT Crystal output, nominally 14.318MHz. Has internal load cap (33pF).
PWR Ground pins for 3.3V supply.
OUT
OUT
IN
OUT
OUT
IN
PWR
IN
IN
I/O
IN
OUT
IN
PWR
OUT
IN
OUT
OUT
IN
OUT
OUT
IN
IN
OUT
3.3V Fixed 66MHz clock outputs for HUB.
3.3V PCI clock output
Hardware enable of watch dog circuit. Enabled when latched high.
3.3V PCI clock output.
3.3V PCI clock outputs.
Asynchronous active low input pin used to power down the device into a low
power state. The internal clocks are disabled and the VCO and the crystal are
stopped. The latency of the power down will not be greater than 3ms.
Analog power 3.3V.
This 3.3V LVTTL input is a level sensitive strobe used to determine when FS (4:0)
inputs are valid and are ready to be sampled (active low).
Clock pin for I²C circuitry 5V tolerant.
Data pin for I²C circuitry 5V tolerant.
Halts PCICLK clocks at logic 0 level, when input low except PCICLK_F which are
free running.
3.3V output selectable through I²C to be 66MHz from internal VCO or
48MHz (non-SSC).
Logic input frequency select bit. Input latched at power on.
Analog power 3.3V.
3.3V Fixed 48MHz clock output for DOT.
Logic input frequency select bit. Input latched at power on.
3.3V Fixed 48MHz clock output for USB.
This pin establishes the reference current for the CPUCLK pairs. This pin requires
a fixed precision resistor tied to ground in order to establish the appropriate
current.
3.3V LVTTL input for selecting the current multiplier for CPU outputs
"Complementory" clocks of differential pair CPU outputs. These are current
outputs and external resistors are required for voltage bias.
"True" clocks of differential pair CPU outputs. These are current outputs and
external resistors are required for voltage bias.
Logic input frequency select bit. Input latched at power on.
Halts CPUCLK clocks at logic 0 level, when input low except CPUCLK_F which
are free running.
3.3V, 14.318MHz reference clock output.
0465E—05/17/05
2