ICS950211 Datasheet, PDF (6/21 Pages) Integrated Circuit Systems – Programmable Timing Control Hub for P4

Integrated
Circuit
Systems, Inc.
ICS950211
Byte 1: Output Control Register
(1 = enable, 0 = disable)
Bit
Pin# PWD
Bit7 44, 45
1 CPUT/C2
Bit6 48, 49
1 CPUT/C1
Bit5 51, 52
1 CPUT/C0
Bit4
-
X FS4 Read back
Bit3
-
X FS3 Read back
Bit2
-
X FS2 Read back
Bit1
-
X FS1 Read back
Bit0
-
X FS0 Read back
Description
Byte 2: Output Control Register
(1 = enable, 0 = disable)
Bit
Pin# PWD
Bit7
-
X MULTSEL (Read back)
Bit6
18
1 PCICLK_6
Bit5
17
1 PCICLK_5
Bit4
16
1 PCICLK_4
Bit3
13
1 PCICLK_3
Bit2
12
1 PCICLK_2
Bit1
11
1 PCICLK_1
Bit0
10
1 PCICLK_0
Description
Byte 3: Output Control Register
(1 = enable, 0 = disable)
Bit
Pin# PWD
Description
Bit7
38
1 48MHZ_DOT
Bit6
39
1 48MHz_USB
Bit5
-
1 Reset gear shift detect 1 = Enable, 0 = Disable
Bit4
-
0 Async freq. control bit 0 (See Async Freq. Control Table)
Bit3
35
0 3V66_1/VCH_CLK, (default) = 66.66MHz, 1=48MHz
Bit2
7
1 PCICLK_F2
Bit1
6
1 PCICLK_F1
Bit0
5
1 PCICLK_F0
Byte 4: Output Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
-
-
33
35
24
23
22
21
PWD
1
X
1
1
1
1
1
1
Description
Async. freq. control bit 1 (See Async. Freq. Control Table)
Reserved
3V66_0
3V66_1/VCH_CLK
3V66_5
3V66_4
3V66_3
3V66_2
Notes:
1. PWD = Power on Default
2. For disabled clocks, they stop low for single ended clocks. Differential CPU clocks stop with CPUCLKT at high,
CPUCLKC off, and external resistor termination will bring CPUCLKC low.
0465E—05/17/05
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