ICS843002I-41 Datasheet, PDF (7/21 Pages) Integrated Circuit Systems – 700MHz, FEMTOCLOCKS-TM VCXO BASED SONET/SDH JITTER ATTENUATOR

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS843002I-41
700MHZ, FEMTOCLOCKS™ VCXO BASED
SONET/SDH JITTER ATTENUATOR
TABLE 6A. AC CHARACTERISTICS, V_CC = V_CCA = V , _{CCO_LVCMOS} V_{CCO_LVPECL} = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical
F_OUT
tjit(ø)
tsk(o)
Output Frequency
RMS Phase Jitter, (Random);
NOTE 1
Output Skew; NOTE 2, 3
155.52MHz, Integration range:
12kHz - 20MHz
19.44
0.81
105
t_R / t_F
Output Rise/Fall Time
20% to 80%
890
odc
Output Duty Cycle
50
See Parameter Measurement Information section.
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
Maximum Units
700
MHz
ps
ps
ps
%
TABLE 6B. AC CHARACTERISTICS, V_CC = V_CCA = 3.3V±5%, V , _{CCO_LVCMOS} V_{CCO_LVPECL} = 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
F_OUT
tjit(ø)
tsk(o)
Output Frequency
RMS Phase Jitter, (Random);
NOTE 1
Output Skew; NOTE 2, 3
155.52 MHz, Integration range:
12kHz - 20MHz
19.44
0.83
95
700
MHz
ps
ps
t_R / t_F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
900
ps
50
%
See Parameter Measurement Information section.
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
843002AKI-41
www.icst.com/products/hiperclocks.html
7
REV. A JUNE 1, 2005