ICS843002I-41 Datasheet, PDF (10/21 Pages) Integrated Circuit Systems – 700MHz, FEMTOCLOCKS-TM VCXO BASED SONET/SDH JITTER ATTENUATOR

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS843002I-41
700MHZ, FEMTOCLOCKS™ VCXO BASED
SONET/SDH JITTER ATTENUATOR
APPLICATION INFORMATION
DESCRIPTION OF THE PLL STAGES
The ICS843002I-41 is a two stage device, a VCXO PLL
followed by a low phase noise FemtoClock PLL. The VCXO
uses an external pullable crystal which can be pulled
±100ppm by the VCXO PLL circuitry to phase lock it to
the input reference frequency. The FemtoClock PLL is a
wide bandwidth PLL (about 800kHz) which means it will
phase track the VCXO PLL. Most of the reference clock
jitter attenuation needs to be accomplished by VCXO PLL.
By using the bypass FemtoClock PLL mode (Table 3B),
the selected input reference clock can be passed directly
to the FemtoClock PLL which will multiply it up by 32 to a
higher frequency. A second mode, VCXO and FemtoClock
bypass, routes the selected input refrence directly to the
LVPECL output dividers.
SETTING THE VCXO PLL LOOP RESPONSE
The VCXO PLL loop response is determined both by fixed
device characteristics and by other characteristics set by the
user. This includes the values of R , C , C and R as shown
SSP
SET
in the External VCXO PLL Components figure on this page.
The VCXO PLL loop bandwidth is approximated by:
NBW (VCXO PLL) =
R_S x I_CP x K_O
32
WHERE:
R_S = Value of resistor R_S in loop filter in Ohms
I_CP = Charge pump current in amps (see table on page 12)
K_O = VCXO Gain in Hz/V
VCXO PLL LOOP RESPONSE CONSIDERATIONS
Loop response characteristics of the VCXO PLL is affected
by the VCXO feedback divider value (bandwidth and damp-
ing factor), and by the external loop filter components
(bandwidth, damping factor, and 2^nd frequency response).
A practical range of VCXO PLL bandwidth is from about
10Hz to about 1kHz. The setting of VCXO PLL bandwidth
and damping factor is covered later in this document. A
PC based PLL bandwidth calculator is also under devel-
opment. For assistance with loop bandwidth suggestions
or value calculation, please contact ICS applications.
The above equation calculates the “normalized” loop bandwidth
(denoted as “NBW”) which is approximately equal to the - 3dB
bandwidth. NBW does not take into account the effects of
damping factor or the second pole imposed by C_P. It does,
however, provide a useful approximation of filter performance.
To prevent jitter on the clock output due to modulation of the
VCXO PLL by the phase detector frequency, the following general
rule should be observed:
ƒ (Phase Detector)
NBW (VCXO PLL) ≤
20
ƒ(Phase Detector) = Input Frequency ÷ (R Divider x 32)
The PLL loop damping factor is determined by:
DF (VCLK) = ^RS x
2
I_CP x C_S x K_O
32
WHERE:
C = Value of capacitor C in loop filter in Farads
S
S
843002AKI-41
www.icst.com/products/hiperclocks.html
10
REV. A JUNE 1, 2005