ICS843002I-41 Datasheet, PDF (11/21 Pages) Integrated Circuit Systems – 700MHz, FEMTOCLOCKS-TM VCXO BASED SONET/SDH JITTER ATTENUATOR

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS843002I-41
700MHZ, FEMTOCLOCKS™ VCXO BASED
SONET/SDH JITTER ATTENUATOR
EXTERNAL VCXO PLL COMPONENTS
In general, the loop damping factor should be 0.7 or greater to
ensure output stability. A higher damping factor will create less
peaking in the passband. A higher damping factor may also
increase lock time and output clock jitter when there is excess
digital noise in the system application, due to the reduced ability
of the PLL to respond to and therefore compensate for phase
noise ingress.
LF1 ₁
32
31
LF0 ₂
C_P
R_S
ISET ₃
C_S
C_P establishes a second pole in the VCXO PLL loop filter. For
higher damping factors (> 1), calculate the value of C_P based on
a C value that would be used for a damping factor of 1.This will
S
minimize baseband peaking and loop instability that can lead to
output jitter.
C_P also dampens VCXO PLL input voltage modulation by the
charge pump correction pulses. A C_P value that is too low will
result in increased output phase noise at the phase detector
frequency due to this. In extreme cases where input jitter is high,
charge pump current is high, and C_P is too small, the VCXO PLL
input voltage can hit the supply or ground rail resulting in non-
linear loop response.
The best way to set the value of C_P is to use the filter response
software under development from ICS (please refer to the
following section). C_P should be increased in value until it just
starts affecting the passband peak.
R_SET
LOOP FILTER RESPONSE SOFTWARE
Online tools to calculate loop filter response (coming soon) at
www.icst.com. Contact your local sales representative if a tool
cannot be found for this product.
The external crystal devices and loop filter components should
be kept close to the device. Loop filter and crystal PCB
connection traces should be kept short and well separated from
each other and from other signal traces. Other signal traces
should not run underneath the device, the loop filter or crystal
components.
NOTES ON SETTING THE VALUE OF C_P
As another general rule, the following relationship should be
maintained between components C_S and C_P in the loop filter:
C_P
=
C_S
20
NOTES ON EXTERNAL CRYSTAL LOAD CAPACITORS
In the loop filter schematic diagram, capacitors are shown be-
tween pins 32 to ground and between pins 31 to ground. These
are optional crystal load capacitors which can be used to cen-
ter tune the external pullable crystal (the crystal frequency can
only be lowered by adding capacitance, it cannot be raised).
Note that the addition of external load capacitors will decrease
the crystal pull range and the Kvco value.
LOSS OF REFERENCE INDICATOR (LOR0 AND LOR1) OUTPUT PINS.
The LOR0 and LOR1 pins are controlled by the internal clock as an “edge”). The LOR output will otherwise be low. The
activity monitor circuits. The clock activity monitor circuits are activity monitor does not flag excessive reference transitions in
clocked by the VCXO PLL phase detector feedback clock.
The LOR output is asserted high if there are three consecutive
feedback clock edges without any reference clock edges (in
an phase detector observation interval as an error.The monitor
only distinguishes between transitions occurring and no transi-
tions occurring.
both cases, either a negative or positive transition is counted
843002AKI-41
www.icst.com/products/hiperclocks.html
11
REV. A JUNE 1, 2005