ICS843002I-41 Datasheet, PDF (1/21 Pages) Integrated Circuit Systems – 700MHz, FEMTOCLOCKS-TM VCXO BASED SONET/SDH JITTER ATTENUATOR

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS843002I-41
700MHZ, FEMTOCLOCKS™ VCXO BASED
SONET/SDH JITTER ATTENUATOR
GENERAL DESCRIPTION
The ICS843002I-41 is a member of the
ICS
HiperClockS™ family of high performance clock
HiPerClockS™ _{solutions from ICS. The ICS843002I-41 is a PLL}
based synchronous clock generator that is
optimized for SONET/SDH line card applications
where jitter attenuation and frequency translation is needed.
The device contains two internal PLL stages that are cascaded
in series. The first PLL stage uses a VCXO which is optimized
to provide reference clock jitter attenuation and to be jitter
tolerant, and to provide a stable reference clock for the 2nd
PLL stage (typically 19.44MHz). The second PLL stage
provides additional frequency multiplication (x32), and it
maintains low output jitter by using a low phase noise
FemtoClock™ VCO. PLL multiplication ratios are selected
from internal lookup tables using device input selection pins.
The device performance and the PLL multiplication ratios are
optimized to support non-FEC (non-Forward Error Correction)
SONET/SDH applications with rates up to OC-48 (SONET)
or STM-16 (SDH). The VCXO requires the use of an external,
inexpensive pullable crystal. VCXO PLL uses external passive
loop filter components which are used to optimize the PLL
loop bandwidth and damping characteristics for the given
line card application.
FEATURES
• (2) Differential LVPECL outputs
• Selectable CLKx, nCLKx differential input pairs
• CLKx, nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL or
single-ended LVCMOS or LVTTL levels
• Maximum output frequency: 700MHz
• FemtoClock VCO frequency range: 560MHz - 700MHz
• RMS phase jitter @ 155.52MHz, using a 19.44MHz crystal
(12kHz to 20MHz): 0.81ps (typical)
• Full 3.3V or mixed 3.3V core/2.5V output supply voltage
• -40°C to 85°C ambient operating temperature
PIN ASSIGNMENT
The ICS843002I-41 includes two clock input ports. Each one
can accept either a single-ended or differential input. Each
input port also includes an activity detector circuit, which
reports input clock activity through the LOR0 and LOR1 logic
output pins. The two input ports feed an input selection mux.
“Hitless switching” is accomplished through proper filter
tuning. Jitter transfer and wander characteristics are
influenced by loop filter tuning, and phase transient
performance is influenced by both loop filter tuning and
alignment error between the two reference clocks.
Typical ICS843002I-41 configuration in SONET/SDH Systems:
• VCXO 19.44MHz crystal
• Loop bandwidth: 50Hz - 250Hz
• Input Reference clock frequency selections:
19.44MHz, 38.88MHz, 77.76MHz, 155.52MHz,
311.04MHz, 622.08MHz
• Output clock frequency selections:
19.44MHz, 77.76MHz, 155.52MHz, 311.04MHz,
622.08MHz, Hi-Z
LF1
LF0
ISET
VCC
CLK0
nCLK0
CLK_SEL
QA_SEL2
32 31 30 29 28 27 26 25
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9 10 11 12 13 14 15 16
LOR0
LOR1
nc
VCCO_LVCMOS
VCCO_LVPECL
nQB
QB
VEE
ICS843002I-41
32-Lead VFQFN
5mm x 5mm x 0.75mm package body
K Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
843002AKI-41
www.icst.com/products/hiperclocks.html
REV. A JUNE 1, 2005
1