ICS843002I-41 Datasheet, PDF (16/21 Pages) Integrated Circuit Systems – 700MHz, FEMTOCLOCKS-TM VCXO BASED SONET/SDH JITTER ATTENUATOR

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS843002I-41
700MHZ, FEMTOCLOCKS™ VCXO BASED
SONET/SDH JITTER ATTENUATOR
SINGLE ENDED CLOCK INPUT INTERFACE
When using a LVCMOS or LVTTL clock driver, the clock
input is connected to the CLKx (CLK0 or CLK1) input pin. The
nCLKx (nCLK0 or nCLK1) pin is left unconnected. To help
reduce interference with the internal VCO circuits, an external
resistor can be placed in series with the clock signal right
near the CLKx input pin. Combined with the input pin
capacitance, this resistor acts as a low pass signal filter.
The typical value for this optional series filter resistor is 100Ω.
This will lower both the amplitude and edge rate of the clock
input signal. In the case of a very short clock trace a series
termination resistor may not be needed.
Series
Termination
Optional
Series
Filter
Resistor
LVTTL or
LVCMOS
(no connection)
CLKx
nCLKx
50kΩ
3.3V
50kΩ
50kΩ
3.3V
CLK
nCLK _Differential
Input Stage
External Circuitry
Internal Device Circuitry
FIGURE 6. SINGLE-ENDED CLOCK INPUT INTERFACE
843002AKI-41
www.icst.com/products/hiperclocks.html
16
REV. A JUNE 1, 2005