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| ICSSSTV16857 Datasheet, PDF (6/8 Pages) Integrated Circuit Systems – DDR 14-Bit Registered Buffer | |||
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ICSSSTV16857
From Output
Under Test
VTT
RL=50W
Test Point
CL = 30 pF
(see Note 1)
Load Circuit
LVCMOS
RESET#
Input
tinact
IDD
(see note 2)
VDD/2
VDD
VDD/2
0V
tact
10%
90% IDDH
IDDL
Voltage and Current Waveforms
Inputs Active and Inactive Times
tw
VIH
Input
VREF
VREF
VIL
Voltage Waveforms - Pulse Duration
Timing
Input
VICR
VI(pp)
Input
tSU
th
VREF
VIH
VREF
VIL
Voltage Waveforms - Setup and Hold Times
Timing
Input
VICR
VICR
VI(pp)
tPHL
tPHL
Output
VOH
VTT
VTT
VOL
Voltage Waveforms - Propagation Delay Times
LVCMOS
VIH
RESET#
Input
VDD/2
VIL
tPHL
Output
VOH
VTT
VOL
Voltage Waveforms - Propagation Delay Times
Parameter Measurement Information (VDD = 2.5V ±0.2V)
Notes: 1. CL incluces probe and jig capacitance.
2. IDD tested with clock and data inputs held at VDD or GND, and Io = 0mA.
3. All input pulses are supplied by generators having the following chareacteristics: PRR â¤10 MHz, Zo=50â¦, input
slew rate = 1 V/ns ±20% (unless otherwise specified).
4. The outputs are measured one at a time with one transition per measurement.
5. VTT = VREF = VDDQ/2
6. VIH = VREF + 310mV (ac voltage levels) for differential inputs. VIH = VDD for LVCMOS input.
7. VIL = VREF -310mV (ac voltage levels) for differential inputs. VIL = GND for LVCMOS input.
8. tPLH and tPHL are the same as tpd
Third party brands and names are the property of their respective owners.
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