ICSSSTV16857 Datasheet, PDF (5/8 Pages) Integrated Circuit Systems – DDR 14-Bit Registered Buffer

ICSSSTV16857
Timing Requirements
(over recommended operating free-air temperature range, unless otherwise noted)
SYMBOL
PARAMETERS
VDD=2.5±0.2V
MIN
TYP
MAX
f_clock Clock frequency
t_PD Clock to output time
t_RST Reset to output time
t_SL Output slew rate
Setup time, fast slew rate ^{2, 4}
t_SU
Setup time, slow slew rate ^{3, 4}
Hold time, fast slew rate ^2,4
T_h
Hold time, slow slew rate ^{3, 4}
133
200
1.1
2.4
2.8
3.1
5
1
1.5
4
Data before CKD , CK#E 0.75 0.018
0.9
Data after CKD , CK#E
0.75 0.145
0.9
Notes: 1 - Guaranteed by design, not 100% tested in production.
2 - For data signal input slew rate =1V/ns.
4 - CLK, CLK# signals input slew rates are =1V/ns.
3 - For data signal input slew rate =0.5V/ns and < 1V/ns.
UNITS
MHz
ns
ns
V/ns
ns
ns
ns
ns
Sw itching Characteristics
(over recom m ended operating free-air tem perature range, unles s otherwis e noted)
SYMBOL
From
To
VD D = 2 .5 ± 0 .2 V
(In p u t)
(Ou tp u t)
MIN
TYP
MAX
f_clock
t_PD
t_ph1
CLK, CLK#
RESET#
133
200
Q
1 .1
2 .4
2 .8
Q
3 .1
5
U N ITS
MH z
ns
ns
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