ICSSSTV16857 Datasheet, PDF (1/8 Pages) Integrated Circuit Systems – DDR 14-Bit Registered Buffer

Integrated
Circuit
Systems, Inc.
ICSSSTV16857
DDR 14-Bit Registered Buffer
Recommended Application:
DDR Memory Modules
Product Features:
• Differential clock signal
• Meets SSTL_2 signal data
• Supports SSTL_2 class I & II specifications
• low-voltage operation
VDD = 2.3V to 2.7V
• 48 pin TSSOP package
Truth Table¹
Inputs
RESET#
L
H
H
CLK
X or
Floating
↑
↑
CLK#
X or
Floating
↓
↓
H
L or H L or H
D
X or
Floating
H
L
X
Q Outputs
Q
L
H
L
Q ⁽²⁾
0
Pin Configuration
Q1
1
48
Q2
2
47
GND
3
46
VDDQ
4
45
Q3
5
44
Q4
6
43
Q5
7
42
GND
8
41
VDDQ
9
40
Q6
10
39
Q7
11
38
VDDQ
12
37
GND
13
36
Q8
14
35
Q9
15
34
VDDQ
16
33
GND
17
32
Q10
18
31
Q11
19
30
Q12
20
29
VDDQ
21
28
GND
22
27
Q13
23
26
Q14
24
25
D1
D2
GND
VDD
D3
D4
D5
D6
D7
CLK#
CLK
VDD
GND
VREF
RESET#
D8
D9
D10
D11
D12
VDD
GND
D13
D14
48-Pin TSSOP & TVSOP
6.10 mm. Body, 0.50 mm. pitch = TSSOP
4.40 mm. Body, 0.40 mm. pitch = TSSOP (TVSOP)
Notes:
1. H = High Signal Level
L = Low Signal Level
↑ = Transition LOW-to-HIGH
↓ = Transition HIGH -to LOW
X = Irrelevant
2. Output level before the indicated
steady state input conditions were
established.
Block Diagram
CLK
CLK#
38
39
RESET# ³⁴
D1
VREF
48
35
R
CLK
D1
1 _Q1
16857 Rev D 07/09/01
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this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.