ICS84330-03 Datasheet, PDF (6/20 Pages) Integrated Circuit Systems – 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

Integrated
Circuit
Systems, Inc.
ICS84330-03
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
TABLE 2. PIN DESCRIPTIONS
Number
Name
Type
Description
1
SCL
Input NOTE 1 I²C serial clock input.
2
SDA
Input NOTE 1 I²C serial data input.
3
ADDR_SEL Input Pulldown Serial address select pin. LVCMOS / LVTTL interface levels.
4, 5
V_CCA
Power
Analog supply pin.
6
FREF_EXT Input Pulldown PLL reference input. LVCMOS / LVTTL interface levels.
Selects between the crystal oscillator or FREF_EXT inputs as the PLL
7
XTAL_SEL Input Pullup reference source. Selects XTAL inputs when HIGH. Selects FREF_EXT
when LOW. LVCMOS / LVTTL interface levels.
8, 9
XTAL_IN,
XTAL_OUT
Input
Crystal oscillator interface. XTAL_IN is an oscillator input.
XTAL_OUT is an oscillator output.
10
OE
Input Pullup Output enable. LVCMOS / LVTTL interface levels.
11
nP_LOAD
12, 13, 14,
15, 17, 18,
19, 20
21
M0, M1, M2
M3, M4, M5
M6, M7
M8
Input
Pullup
Parallel load input. Determines when data present at M8:M0 is loaded
into M divider, and when data present at N1:N0 sets the N output divide
value. LVCMOS / LVTTL interface levels.
Input
Input
Pulldown _{M divider inputs. Data latched on LOW-to-HIGH transition of nP_LOAD}
input. LVCMOS / LVTTL interface levels.
Pullup
16
22, 23
24
nc
N0, N1
VCO_SEL
Unused
Input
Input
Pulldown
Pullup
No connect.
Determines N output divider value as defined in Table 4B Function
Table. LVCMOS / LVTTL interface levels.
When logic LOW, bypass PLL. When logic HIGH, PLL is active.
LVCMOS/LVTTL interface levels.
25, 29
26, 32
27, 28
V_EE
V_CC
nQ1, Q1
Power
Power
Output
Negative supply pins.
Core supply pins.
Differential clock outputs. LVPECL interface levels.
30, 31
nQ0, Q0 Output
Differential clock outputs. LVPECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 3, Pin Characteristics, for typical values.
NOTE 1: Pullup resistor is only active in parallel mode.
TABLE 3. PIN CHARACTERISTICS
Symbol
C_IN
R_PULLUP
R_PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
84330AY-03
www.icst.com/products/hiperclocks.html
6
REV. A FEBRUARY 2, 2006