ICS84330-03 Datasheet, PDF(3/20 Page) Integrated Circuit Systems – 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

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ICS84330-03 Datasheet, PDF (3/20 Pages) Integrated Circuit Systems – 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

◁

Integrated

Circuit

Systems, Inc.

ICS84330-03

700MHZ, LOW JITTER, CRYSTAL-TO-3.3V

DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

I2C INTERFACE - PROTOCOL

The ICS84330-03 is a slave-only device and uses the stan-

dard I2C protocol as shown in the below diagrams. The maxi-

mum SCL frequency is greater than 10MHz which is more

than sufficient for standard I2C clock speeds.

SCL

SDA

START

Valid Data

Acknowledge

START (ST) â defined as high-to-low transition on SDA while holding SCL HIGH.

DATA - Between START and STOP cycles, SDA is synchronous with SCL.

Data may change only when SCL is LOW and must be stable when SCL is HIGH.

ACKNOWLEDGE (AK) â SDA is driven LOW before the SCL rising edge and

held LOW until the SCL falling edge.

STOP (SP) â defined as low-to-high transition on SDA while holding SCL HIGH.

STOP

I2C INTERFACE - A WRITE EXAMPLE

A serial transfer to the ICS84330-03 always consists of an

address cycle followed by 4 data bytes: 1 dummy byte fol-

lowed by 3 data bytes. Any additional bytes beyond the 4 data

bytes will not be acknowledged and the ICS84330-03 will

leave the data bus HIGH. These extra bits will not be loaded

into the serial control register. Once the 4 Data bytes are loaded

and the master generates a stop condition, the values in the

serial control register are latched into the M divider, N divider,

and control bits and the device will smoothly slew to the new

frequency and any changes to the state of the control bits will

take effect.

Slave Address: 7 Bits

1 Bit Refer to page 2 for address choices based on ADDR_SEL pin setting

R/W

1 Bit

Dummy Byte 0: 8 Bits

1 Bit

Data Byte 0: 8 Bits

1 Bit

Data Byte 1: 8 Bits

Not

Used

Used Used 1 Bit

84330AY-03

Down

Data Byte 2: 8 Bits

SSC5 SSC4 SSC3 SSC2 SSC1 SSC0 1 Bit 1 Bit

Data Byte values latched into control registers here.

www.icst.com/products/hiperclocks.html

REV. A FEBRUARY 2, 2006

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