ICS84330-03 Datasheet, PDF (4/20 Pages) Integrated Circuit Systems – 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

Integrated
Circuit
Systems, Inc.
ICS84330-03
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
SPREAD SPECTRUM OPERATION
NOTE: The functional description that follows used a
16.6667MHz crystal with an M divide value of 160.
Spread Spectrum operation is controlled by I²C Data Byte
2, Spread Spectrum Control Register. Bits SSC0 – SSC5
(SS) of the register are a subtrahend to the M-divider for
down-spread, and they are an addend and a subtrahend to
the M-divider for center-spread. When the UP bit is HIGH,
then up-spread has been selected and the M-divider value
will toggle between the programmed M value, and M+SS at
a 32kHz rate. When the DN bit is HIGH, then down-spread
has been selected and the M-divider value will toggle be-
tween the programmed M value, and M-SS at a 32kHz rate.
When both the UP and DN bits are HIGH, then center-
spread has been selected and the M-divider will toggle
between M+SS and M-SS at a 32kHz rate. The table below
shows the desired SS value to achieve 0.5%, 1% and 1.5%
spread at selected VCO frequencies. To disable Spread
Spectrum operation, program both the UP and DN bits to
LOW. Spread Spectrum operation will also be disabled when
the nP_LOAD input is LOW.
TABLE 1A. SS MODE FUNCTION TABLE
Register Bits
SSC7
0
0
1
SSC6
0
1
0
1
1
SS Mode
Off
Down-Spread
Up-Spread
Center-Spread
TABLE 1B. UP/DOWN SPREAD CONFIGURATION
SSC5
0
0
0
0
0
0
0
0
Up- or Down-Spread SS Value
SSC4
0
SSC3
0
SSC2
0
SSC1
0
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
SSC0
1
0
0
0
0
0
0
0
Spread %
0.50
1.00
1.50
2.00
2.50
3.00
3.50
4.00
TABLE 1C. CENTER SPREAD CONFIGURATION
Center-Spread SS Value
SSC5
0
0
0
0
SSC4
0
0
0
0
SSC3
0
0
0
1
SSC2
0
1
1
0
SSC1
0
0
1
0
SSC0
1
0
0
0
Spread (±) %
0.50
1.00
1.50
2.00
84330AY-03
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REV. A FEBRUARY 2, 2006