ICS84330-03 Datasheet, PDF (2/20 Pages) Integrated Circuit Systems – 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

Integrated
Circuit
Systems, Inc.
ICS84330-03
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
The ICS84330-03 uses either a parallel interface or indus-
try standard I²C interface to control the programming of the
internal dividers. The power on defaults are summarized as
follows:
M
Parallel Mode: 256
Output
Q0/nQ0 output at 267MHz
(using a 16.667MHz crystal)
Q1/nQ1 output at 133MHz
(using a 16.667MHz crystal)
The programming mode is controlled by the nP_LOAD pin.
When this pin is low, The M, N values are set by the logic
values on the M, N pins. If nP_LOAD is HIGH, the M, N
dividers can be changed using the I²C serial programming
interface.
The I²C control registers are defined below:
SSC Mode:
Off
Data Byte 0
Control Bit
N1
N0
M8
M7
M6
M5
M4
M3
Power-up Default Value
0
0
1
0
0
0
0
0
Data Byte 1
Control Bit
M2
M1
M0
Not Not Not Not Not
Used Used Used Used Used
Power-up Default Value
0
0
0
X
X
X
X
X
Data Byte 2
Control Bit
Power-up Default Value
Up Down SSC5 SSC4 SSC3 SSC2 SSC1 SSC0
0
0
0
0
0
0
0
0
I²C ADDRESSING
The ICS84330-03 can be set to decode one of two addresses
to minimize the chance of address conflict on the I²C bus. The
address that is decoded is controlled by the setting of the
ADDR_SEL pin (pin 3).
Bit 7
1
Bit 6
1
ADDR_SEL (pin 3) = 0 Default
Bit 5 Bit 4 Bit 3 Bit 2
0
1
1
0
Bit 1
0
Bit 0
R/W
Bit 7
1
Bit 6
1
ADDR_SEL (pin 3) = 1
Bit 5 Bit 4 Bit 3 Bit 2
0
1
1
1
Bit 1
0
Bit 0
R/W
84330AY-03
www.icst.com/products/hiperclocks.html
2
REV. A FEBRUARY 2, 2006