ICS527-04 Datasheet, PDF (5/9 Pages) Integrated Circuit Systems – Clock Slicer User Configurable PECL input Zero Delay Buffer

ICS527-04
Clock Slicer User Configurable PECL input Zero Delay Buffer
Multiple Output Example
In this example, an input clock of 125 MHz is used. Four low skew copies of 50 MHz PECL are required
aligned to the 125 MHz input clock. The following solution uses the ICS554-01A, which is a 1 to 4 PECL
buffer with low pin to pin skew.
VDD
0.01 F
50 MHz
125 MHz
125 MHz
R5
R6
IRANGE
S0
S1
VDD
FBPECL
FBPECL
GND
PECLIN
PECLIN
F0
F1
F2
R4
R3
R2
R1
R0
VDD
PECLO
PECLO
GND
RES
F6
F5
F4
F3
0.01 F
RN
RN
560
OE
VDD
RN
Q0
RN
Q0
0.01 F
RN
Q1
RN
Q1
GND
IN
NC
VDD
Q3
RN
Q3
RN
0.01 F
Q2
RN
Q2
RN
GND
IN
The layout design above produces the waveforms shown below.
125 MHz, PECLIN
50 MHz, PECLO
(Complementary outputs are not shown)
Using the equation for selecting dividers gives:
(FDW + 2)
50 MHz = 125 MHz *
(RDW + 2)
If FDW = 0, then RDW = 3. This gives the required divide-by-5 function. Setting pin IRANGE = 1 (by leaving
it unconnected and using the internal pull-up) allows a higher speed input clock like the 125 MHz. The
FBPECL pair pins are connected to the Q1 outputs (chosen arbitrarily) of the ICS554. This aligns all the
outputs of the ICS554 with the 125 MHz input since the ICS527-04 aligns rising edges on the PECLIN and
FBPECL pins.
In this example, the resistor network needed for each PECLO output is represented by the RN boxes.
MDS 527-04 D
5
Revision 122804
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