ICS527-04 Datasheet, PDF (4/9 Pages) Integrated Circuit Systems – Clock Slicer User Configurable PECL input Zero Delay Buffer

ICS527-04
Clock Slicer User Configurable PECL input Zero Delay Buffer
Typical Example
The following connection diagram shows the implementation of the example from the previous section.
This will generate a 50 MHz clock synchronously with a 40 MHz input. The layout diagram below will
produce the waveforms shown on the bottom of the example.
VDD
0.01 F
40 MHz
40 MHz
R5
R6
IRANGE
S0
S1
VDD
FBPECL
FBPECL
GND
PECLIN
PECLIN
F0
F1
F2
R4
R3
R2
R1
R0
VDD
PECL
PECL
GND
RES
F6
F5
F4
F3
0.01 F
560
VDD
50 MHz
180
PECL output resistor network (50 ohm) is not
shown, but is identical to PECL
40 MHz
(PECLIN shown)
50 MHz PECL
50 MHz PECL
MDS 527-04 D
4
Revision 122804
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