ICS527-04 Datasheet, PDF (1/9 Pages) Integrated Circuit Systems – Clock Slicer User Configurable PECL input Zero Delay Buffer

ICS527-04
Clock Slicer User Configurable PECL input Zero Delay Buffer
Description
The ICS527-04 Clock Slicer is the most flexible way to
generate an output clock from an input clock with zero
skew. The user can easily configure the device to
produce nearly any output clock that is multiplied or
divided from the input clock. The part supports
non-integer multiplications and divisions. Using
Phase-Locked Loop (PLL) techniques, the device
accepts an input clock up to 200 MHz and produces an
output clock up to 160 MHz.
The ICS527-04 aligns rising edges on PECLIN with
FBPECL at a ratio determined by the reference and
feedback dividers.
For other PECL output clocks, see the ICS507-01,
ICS525-03, or the MK3707. For PECL in and CMOS
out, see the ICS527-02. For CMOS in and PECL out
with zero delay, use the ICS527-03.
Features
• Packaged as 28-pin SSOP (150 mil body)
• Synchronizes fractional clocks rising edges
• CMOS in to PECL out
• PECL in to PECL out
• Pin selectable dividers
• Zero input to output skew
• User determines the output frequency - no software
needed
• Slices frequency or period
• Input clock frequency of 1.5 MHz - 200 MHz
• Output clock frequencies up to 160 MHz
• Very low jitter
• Duty cycle of 45/55
• Operating voltage of 3.3 V
• Advanced, low power CMOS process
Block Diagram
PECLIN
PECLIN
Divide
by 2
1
0
R6:R0
7
Reference
Divider
FBPECL
FBPECL
Divide
by 2
1
0
Feedback
Divider
IRANGE
7
F6:F0
2 VDD
560 ohm
RES
VDD
Phase Comparator,
Charge Pump, and
Loop Filter
VCO
Output
Divider
2 _GND
2
S1:S0
VDD
68 ohm
PECLO
180 ohm
VDD
68 ohm
180 ohm
PECLO
MDS 527-04 D
1
Revision 122804
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel [phone] ● www.icst.com