ICS527-04 Datasheet, PDF (2/9 Pages) Integrated Circuit Systems – Clock Slicer User Configurable PECL input Zero Delay Buffer

ICS527-04
Clock Slicer User Configurable PECL input Zero Delay Buffer
Pin Assignment
R5
1
R6
2
IR A N G E
3
S0
4
S1
5
VDD
6
FBPECL
7
FBPECL
8
GND
9
P E C L IN
10
P E C L IN
11
F0
12
F1
13
F2
14
28
R4
27
R3
26
R2
25
R1
24
R0
23
VDD
22
PECLO
21
PECLO
20
GND
19
RES
18
F6
17
F5
16
F4
15
F3
28-pin (150 mil) SSOP
Output Frequency and Output
Divider Table
S1
Pin 5
0
0
1
1
S0
Pin 4
0
1
0
1
Output Frequency (MHz)
PECLO Output Pair
10 - 80
5 - 40
2.5 - 20
20 -160
IRANGE Setting Table
IRANGE
Criteria
0
if (FBPECL < 80 MHz) and (PECLIN < 80 MHz)
1
if (FBPECL > 80 MHz) or (PECLIN > 80 MHz)
Pin Descriptions
Pin
Number
1-2
24 - 28
3
4-5
6, 23
7
8
9, 20
10
11
12 - 18
19
21
22
Pin
Name
R5, R6,
R0-R4
IRANGE
S0, S1
VDD
FBPECL
FBPECL
GND
PECLIN
PECLIN
F0-F6
RES
PECLO
PECLO
Pin
Type
Input
Input
Input
Power
Input
Input
Power
Input
Input
Input
BIAS
Output
Output
Pin Description
Reference divider word input pins determined by user. Forms a binary number
from 0 to 127. Internal pull-up.
Set for proper frequency range of input clocks. See table above.
Select pins for output frequency range. See table above. Internal pull-up.
Connect to +3.3 V.
PECL feedback input to PLL.
PECL feedback input to PLL.
Connect to ground
PECL input clock.
Complementary PECL input clock.
Feedback divider word input pins determined by user. Forms a binary number
from 0 to 127. Internal pull-up
Resistor connection to VDD for setting level of PECL outputs.
Complementary PECL output.
PECL output. Rising edge aligns with PECLIN when connected directly to
FBPECL.
MDS 527-04 D
2
Revision 122804
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