ICS1562B Datasheet, PDF (3/20 Pages) Integrated Circuit Systems – User Programmable Differential Output Graphics Clock Generator

ICS1562B
This allows the synthesizer to be completely programmed for
the desired frequency before it is made active. Once the part
has been “unlocked” by the 32 writes, programming becomes
effective immediately.
ALL registers identified in the data sheet (0-9, 11, 12 & 15)
MUST be written upon initial programming. The programming
registers are not initialized upon power-up, but the latched
outputs of those registers are. The latch is made transparent
after 32 register writes. If any register has not been written, the
state upon power-up (random) will become effective. Registers
13 & 14 physically do not exist. Register 10 does exist, but is
reserved for future expansion. To insure compatibility with
possible future modifications to the database, ICS recommends
that all three unused locations be written with zero.
STROBE
AD0-AD3
ICS1562B-001 Register Loading
5
1
2
ADDRESS VALID
3
4
DATA VALID
Figure 2
Digital Inputs - ICS1562B-201 Option
The programming of the ICS1562B-201 is performed serially
by using the DATCLK, DATA, and HOLD~pins to load an
internal shift register.
DATA is shifted into the register on the rising edge of
DATCLK. The logic value on the HOLD~pin is latched at the
same time. When HOLD~ is low, the shift register may be
loaded without disturbing the operation of the ICS1562B.
When high, the shift register outputs are transferred to the
control registers, and the new programming information be-
comes active. Ordinarily, a high level should be placed on the
HOLD~ pin when the last data bit is presented. See Figure 3
for the programming sequence.
DATCLK
DATA
HOLD
ICS1562B-201 Register Loading
8
6
7
DATA_1
DATA_2
DATA_56
Figure 3
An additional control pin on the ICS1562B-201, BLANK can
perform either of two functions. It may be used to disable the
phase-frequency detector in line-locked applications. Alterna-
tively, the BLANK pin may be used as a synchronous enable
for VRAM shift clock generation. See sections on Line-Locked
Operations and VRAM shift clock generation for details.
Output Description
The differential output drivers, CLK+ and CLK, are current-
mode and are designed to drive resistive terminations in a
complementary fashion. The outputs are current-sinking only,
with the amount of sink current programmable via the IPRG
pin. The sink current, which is steered to either CLK+or CLK-,
is four times the current supplied to the IPRG pin. For most
applications, a resistor from VDDO to IPRG will set the current
to the necessary precision. Additionally, minor adjustment to
the duty factor can be achieved under register control.
The LOAD output is a high-current CMOS type drive whose
frequency is controlled by a programmable divider that may be
selected for a modulus of 3, 4, 5, 6, 8, 10, 12, 16 or 20. It may
also be suppressed under register control. The load output may
be programmed to output the VCO frequency divided by 2 (see
AUX_N1 description in Register Mapping section), inde-
pendent of the differential output and N1 divider modulus.
The LD/N2 output is high-current CMOS type drive whose
frequency is derived from the LOAD output. The programma-
ble modulus may range from 1 to 512 in steps of one.
3