ICS1562B Datasheet, PDF (10/20 Pages) Integrated Circuit Systems – User Programmable Differential Output Graphics Clock Generator

ICS1562B
REG#
11
BIT(S)
0-1
11
2
11
3
12
0
12
1
12
2
12
3
15
0
15
3
BIT REF.
S[0]..S[1]
DESCRIPTION
PLL post-scaler/test mode select bits
S[1] S[0]
DESCRIPTION
0 0 Post-scaler=1. F(CLK)=F(PLL). The output of the N1 divider
drives the LOAD output which, in turn, drives the N2 divider.
0 1 Post-scaler=2. F(CLK)=F(PLL)/2. The output of the N1 divider
drives the LOAD output which, in turn, drives the N2 divider.
1 0 Post-scaler=4. F(CLK)=F(PLL)/4. The output of the N1 divider
drives the LOAD output which, in turn, drives the N2 divider.
1 1 AUXEN CLOCK MODE. The AUXCLK bit drives the differential
outputs CLK+ and CLK- and the AUXN1 bit drives the LOAD
output which, in turn, drives the N2 divider.
AUX_CLK
AUX_N1
RESERVED
JAMPLL
DACRST
SELXTAL
ALTLOOP
PDRSTEN
When in the AUXEN clock mode, this bit controls the differential
outputs.
When in the AUXEN clock mode, this bit controls the LOAD output
(and consequently the N2 output according to its programming).
When not in the AUXEN clock mode, this bit, if set to one, will over-
ride the N1 divider modulus and output the VCO frequency divided
by two [F(PLL)/2] at the LOAD output.
Must be set to zero.
Tristates phase detector outputs; resets phase detector logic, and
resets R, A, M, and N2 counters.
Set to zero for normal operation. When set to one, the CLK+output
is kept high and the CLK- output is kept low. (All other device func-
tions are unaffected.) When returned to zero, the CLK+ and CLK-
outputs will resume toggling on a rising edge of the LD output
(+/- 1 CLK period). To initiate a RAMDAC reset sequence,
simply write a one to this register bit followed by a zero.
When set to logic 1, passes the reference frequency to the post-scaler.
Controls substitution of N1 and N2 dividers into feedback loop of PLL.
When this bit is a logic 1, the N1 and N2 dividers are used.
Phase-detector reset enable control bit. When this bit is set, the AD3
pin becomes a transparent reset input to the phase detector.
See "Internal Feedback Operation" section for more
details on the operation of this function.
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