ICS1562B Datasheet, PDF (17/20 Pages) Integrated Circuit Systems – User Programmable Differential Output Graphics Clock Generator

ICS1562B
AC Characteristics
SYMBOL
Fvco
Fxtal
Cpar
Fload
Txhi
Txlo
Tlock
Idd
Iddo
Thigh
Jclk
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PARAMETER
MIN
VCO Frequency (see Note 1)
40
Crystal Frequency
5
Crystal Oscillator Loading Capacitance
LOAD Frequency
XTAL1 High Time (when driven externally)
8
XTAL1 Low Time (when driven externally)
8
PLL Acquire Time (to within 1%)
VDD Supply Current
VDDO Supply Current (excluding CLK+/−
termination)
Differential Clock Output Duty Cycle
45
(see Note 2)
Differential Clock Output Cumulative Jitter
(see Note 3)
DIGITAL INPUTS - ICS1562B-001
Address Setup Time
10
Address Hold Time
10
Data Setup Time
10
Data Hold Time
10
STROBE Pulse Width (Thi or Tlo)
20
DIGITAL INPUTS - ICS1562B-201
DATA/HOLD~ Setup Time
10
DATA/HOLD~ Hold Time
10
DATCLK Pulse Width (Thi or Tlo)
20
PIPELINE DELAY RESET
Reset Activation Time
Reset Duration
4*Tload
Restart Delay
Restart Matching
-1*Tclk
DIGITAL OUTPUTS
CLK+/CLK− Clock Rate
LOAD To LD/N2 Skew (Shift Clock Mode)
-2
TYP
20
500
15
20
<0.06
0
MAX
260
20
80
t.b.d.
t.b.d.
55
UNITS
MHz
MHz
pf
MHz
ns
ns
µs
mA
mA
%
pixel
2*Tclk
2*Tload
+1.5*Tclk
260
+2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
Note 1: Use of the post-divider is required for frequencies lower than 40 MHz on CLK+ & CLK- outputs. Use of the post-divider
is recommended for output frequencies lower than 65 MHz.
Note 2: Using load circuit of Figure 6. Duty cycle measured at zero crossings of difference voltage between CLK+ and CLK-.
Note 3: Cumulative jitter is defined as the maximum error (in the domain) if any CLK edge, at any point in time, compared with
the equivalent edge generated by an ideal frequency source.
ICS laboratory testing indicates that the typical value shown above can be treated as a maximum jitter specification in
virtually all applications. Jitter performance can depend somewhat on circuit board layout, decoupling, and register
programming.
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